Sylpheed/tools/ppc-manual/fpu/fmaddx.md

fmaddx — Floating Multiply-Add

Category: Floating-Point · Form: A · Opcode: 0xfc00003a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fmadd	fmaddx	—	Floating Multiply-Add
fmadd.	fmaddx	Rc=1	Floating Multiply-Add

Syntax

fmadd[Rc] [FD], [FA], [FC], [FB]

Encoding

fmaddx — form A

• Opcode word: 0xfc00003a
• Primary opcode (bits 0–5): 63
• Extended opcode: 29
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fmaddx: read	Source A floating-point register (fr0–fr31).
FC	fmaddx: read	Source C floating-point register (for madd-style ops).
FB	fmaddx: read	Source B floating-point register.
FD	fmaddx: write	Destination floating-point register.
CR	fmaddx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fmaddx: write	Floating-Point Status and Control Register.

Register Effects

fmaddx

• Reads (always): FA, FC, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fmaddx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

FRT <- (FRA × FRC) + FRB

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fmaddx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fmaddx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:186
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:77
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1043

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fmaddx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_fmadd(f, i, false);
}

Special Cases & Edge Conditions

• Single rounding step. fmadd computes (FRA × FRC) + FRB with one IEEE-754 rounding at the end — strictly more accurate than separate multiply + add. Canary matches that only on hosts with FMA3, where it emits vfmadd213sd; without FMA3 it falls back to vmulsd + vaddsd, which rounds twice and can differ in the last bit.
• Operand layout. A-form: FRT, FRA, FRC, FRB. Note the assembler order — FRC (multiplier) comes before FRB (addend). Encoding bit fields are FRA (11–15), FRB (16–20), FRC (21–25).
• Invalid operations. 0×∞ + finite → VXIMZ; ∞×x + ∓∞ (after multiplication produces ±∞ that opposes addend sign) → VXISI. Quiet NaN result with FPSCR[VX, FX] set.
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX, OX, UX, XX, VXIMZ, VXISI, VXSNAN. Canary does not update FPSCR (UpdateFPSCR is a stub).
• Rc=1 (fmadd.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Use case. Dot products, polynomial evaluation (Horner's method), matrix multiplies, Newton-Raphson divide/sqrt refinement. Hot-path PPC code is dense with fmadd.
• Denormal flush. That Xenon boots with FPSCR[NI]=1 is unverified. Canary starts every guest thread in IEEE mode (MXCSR 0x1F80; its init comment flags the startup state as unchecked) and turns on the host's flush-to-zero (MXCSR.FZ) only when the guest sets NI through mtfsf/mtfsfi.

Related Instructions

• fmaddsx — single-precision sibling.
• fmsubx, fnmaddx, fnmsubx — the other three fused multiply-add variants:
  • fmsub = (A×C) − B
  • fnmadd = −((A×C) + B)
  • fnmsub = −((A×C) − B)
• fmulx, faddx — non-fused decomposition (two rounding steps; less precise).
• fresx, frsqrtex — reciprocal helpers refined by fmadd/fnmsub.

IBM Reference

• AIX 7.3 — fmadd (Floating Multiply-Add)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (single-rounding fused multiply-add definition).