Sylpheed/tools/ppc-manual/fpu/fresx.md

fresx — Floating Reciprocal Estimate Single

Category: Floating-Point · Form: A · Opcode: 0xec000030

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fres	fresx	—	Floating Reciprocal Estimate Single
fres.	fresx	Rc=1	Floating Reciprocal Estimate Single

Syntax

fres[Rc] [FD], [FB]

Encoding

fresx — form A

• Opcode word: 0xec000030
• Primary opcode (bits 0–5): 59
• Extended opcode: 24
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FB	fresx: read	Source B floating-point register.
FD	fresx: write	Destination floating-point register.
CR	fresx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fresx: write	Floating-Point Status and Control Register.

Register Effects

fresx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fresx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fresx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fresx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:106
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:89
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:505

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fresx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- 1.0 / (frB)

  // this actually does seem to require single precision, oddly
  // more research is needed
  Value* v = f.Recip(f.Convert(f.LoadFPR(i.A.FRB), FLOAT32_TYPE));
  v = f.Convert(v, FLOAT64_TYPE);  // f.ToSingle(v);
  f.StoreFPR(i.A.FRT, v);
  f.UpdateFPSCR(v, i.A.Rc);
  return 0;
}

Special Cases & Edge Conditions

• Single-precision reciprocal estimate. PowerISA specifies a low-precision estimate of 1/FRB, correct to one part in 256, intended as the seed for a Newton-Raphson refinement step. Canary quirk: it rounds FRB to binary32 and divides exactly (vdivss into 1.0; its comment rejects AVX-512 vrcp14ss for precision), so it returns a correctly rounded single-precision reciprocal — far more accurate than hardware. Title code that depends on the limited precision of fres to trigger refinement loops will still work (the loops just refine an already-correct value), but bit-exact correlation with hardware is impossible.
• Single precision result. Final value is rounded to binary32 then re-encoded into the FPR.
• Divide by zero. 1/±0 → ±∞ and sets FPSCR[ZX, FX]. Canary returns the host ±∞ but does not update FPSCR.
• fres(±∞) = ±0 (correctly signed).
• fres(NaN) = NaN; signalling NaNs are quietened.
• Overflow / underflow. May set OX/UX/XX/FX. Canary does not update FPSCR.
• Rc=1 (fres.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• Encoding. A-form, primary 59, XO 24. Reads FRB only; FRA/FRC are don't-care.
• Use case. Software reciprocal: 1/d ≈ x = fres(d); x = x*(2 - d*x); (one Newton-Raphson step recovers full single precision). Two iterations recover full double precision. The (2 - d*x) step compiles to fnmsub.
• Performance. Cheap on Xenon (single-cycle issue) — divides by fres + 1–2 NR steps + fmul are far faster than fdiv/fdivs.

Related Instructions

• frsqrtex — reciprocal-square-root estimate; same NR refinement approach.
• fdivx, fdivsx — true divide; alternative when refinement isn't needed.
• fnmsubx, fnmsubsx — the workhorse for the (2 - d*x) step.
• fmulx, fmulsx — final multiply to apply the reciprocal.
• fmaddsx — alternate refinement formulation.

IBM Reference

• AIX 7.3 — fres (Floating Reciprocal Estimate Single)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (relative-error bound for fres; intended Newton-Raphson refinement pattern).