Sylpheed/tools/ppc-manual/fpu/fdivsx.md

fdivsx — Floating Divide Single

Category: Floating-Point · Form: A · Opcode: 0xec000024

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fdivs	fdivsx	—	Floating Divide Single
fdivs.	fdivsx	Rc=1	Floating Divide Single

Syntax

fdivs[Rc] [FD], [FA], [FB]

Encoding

fdivsx — form A

• Opcode word: 0xec000024
• Primary opcode (bits 0–5): 59
• Extended opcode: 18
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fdivsx: read	Source A floating-point register (fr0–fr31).
FB	fdivsx: read	Source B floating-point register.
FD	fdivsx: write	Destination floating-point register.
CR	fdivsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fdivsx: write	Floating-Point Status and Control Register.

Register Effects

fdivsx

• Reads (always): FA, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fdivsx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fdivsx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fdivsx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:71
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:74
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:501

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fdivsx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- frA / frB
#if XE_PLATFORM_LINUX
  // TODO(has207): verify if this is needed on Windows
  // On Linux, fdivs needs to use A format fields instead of X format
  Value* v = f.Div(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRB));
  v = f.ToSingle(v);
  f.StoreFPR(i.A.FRT, v);
  f.UpdateFPSCR(v, i.A.Rc);
#else
  Value* v = f.Div(f.LoadFPR(i.X.RA), f.LoadFPR(i.X.RB));
  v = f.ToSingle(v);
  f.StoreFPR(i.X.RT, v);
  f.UpdateFPSCR(v, i.X.Rc);
#endif
  return 0;
}

Special Cases & Edge Conditions

• Single precision. Result is rounded to IEEE-754 binary32 then re-encoded into the 64-bit FPR. Canary computes ToSingle(Div(a, b)): vdivsd, then vcvtsd2ss + vcvtss2sd under the host rounding mode.
• Divide by zero. Finite/±0 sets FPSCR[ZX, FX] and yields ±∞. Canary returns the host ±∞ but sets no FPSCR bit (UpdateFPSCR is a stub).
• 0 / 0 → FPSCR[VXZDZ, VX, FX], quiet NaN result.
• ±∞ / ±∞ → FPSCR[VXIDI, VX, FX], quiet NaN result.
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX, plus exception bits OX, UX, XX, ZX, VXZDZ, VXIDI, VXSNAN.
• Rc=1 (fdivs.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Single-precision overflow returns ±∞ and sets OX/XX/FX.
• Performance. Hardware divide is multi-cycle. Title code commonly uses fres + Newton-Raphson for hot loops; this instruction is reserved for non-critical paths.
• Denormal flush. That Xenon boots with FPSCR[NI]=1 is unverified. Canary starts every guest thread in IEEE mode (MXCSR 0x1F80; its init comment flags the startup state as unchecked) and turns on the host's flush-to-zero (MXCSR.FZ) only when the guest sets NI through mtfsf/mtfsfi.
• Encoding. A-form, primary 59, XO 18.

Related Instructions

• fdivx — double-precision sibling.
• fresx — reciprocal estimate, used to build software divides.
• fmulsx, faddsx, fsubsx — companion single-precision arithmetic.
• fmaddsx, fnmsubsx — Newton-Raphson refinement helpers.
• frspx — explicit double→single rounding.

IBM Reference

• AIX 7.3 — fdivs (Floating Divide Single)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.