Sylpheed/tools/ppc-manual/fpu/fmaddsx.md

fmaddsx — Floating Multiply-Add Single

Category: Floating-Point · Form: A · Opcode: 0xec00003a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fmadds	fmaddsx	—	Floating Multiply-Add Single
fmadds.	fmaddsx	Rc=1	Floating Multiply-Add Single

Syntax

fmadds[Rc] [FD], [FA], [FC], [FB]

Encoding

fmaddsx — form A

• Opcode word: 0xec00003a
• Primary opcode (bits 0–5): 59
• Extended opcode: 29
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fmaddsx: read	Source A floating-point register (fr0–fr31).
FC	fmaddsx: read	Source C floating-point register (for madd-style ops).
FB	fmaddsx: read	Source B floating-point register.
FD	fmaddsx: write	Destination floating-point register.
CR	fmaddsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fmaddsx: write	Floating-Point Status and Control Register.

Register Effects

fmaddsx

• Reads (always): FA, FC, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fmaddsx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fmaddsx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fmaddsx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:190
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:76
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:508

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fmaddsx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_fmadd(f, i, true);
}

Special Cases & Edge Conditions

• Single rounding step then single-precision rounding. PowerISA semantics: compute (FRA × FRC) + FRB to infinite precision, then round once to binary32. Canary rounds twice — the multiply-add in binary64 (vfmadd213sd on FMA3 hosts, vmulsd + vaddsd otherwise), then ToSingle to binary32. With FMA3 the result can differ only when the binary64 intermediate lands exactly on a binary32 tie under round-to-nearest; the non-FMA fallback also rounds the product on its own.
• Operand order. Assembler: FD, FA, FC, FB (multiplier FRC before addend FRB).
• Invalid operations. 0×∞ + finite → VXIMZ; opposite-signed-∞ collision → VXISI. Quiet NaN result with FPSCR[VX, FX].
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX, OX, UX, XX, VXIMZ, VXISI, VXSNAN. Canary does not (UpdateFPSCR is a stub).
• Rc=1 (fmadds.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Single-precision overflow of the final rounded result returns ±∞ and sets OX/XX/FX.
• Use case. Dominates single-precision graphics math: matrix–vector multiplies, dot products, lighting equations, normal-map blending. Xbox 360 titles emit fmadds constantly.
• Denormal flush. That Xenon boots with FPSCR[NI]=1 is unverified. Canary starts every guest thread in IEEE mode (MXCSR 0x1F80; its init comment flags the startup state as unchecked) and turns on the host's flush-to-zero (MXCSR.FZ) only when the guest sets NI through mtfsf/mtfsfi.

Related Instructions

• fmaddx — double-precision sibling.
• fmsubsx, fnmaddsx, fnmsubsx — single-precision fused-multiply siblings:
  • fmsubs = (A×C) − B
  • fnmadds = −((A×C) + B)
  • fnmsubs = −((A×C) − B)
• fmulsx, faddsx — non-fused decomposition.
• fresx, frsqrtex — reciprocal helpers; Newton-Raphson refinement uses fmadds/fnmsubs.
• frspx — explicit double→single rounding.

IBM Reference

• AIX 7.3 — fmadds (Floating Multiply-Add Single)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.