Sylpheed/tools/ppc-manual/memory/lvlx.md

lvlx — Load Vector Left Indexed

Category: Memory · Form: X · Opcode: 0x7c00040e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lvlx	lvlx	—	Load Vector Left Indexed
lvlx128	lvlx128	—	Load Vector Left Indexed 128

Syntax

lvlx [VD], [RA0], [RB]
lvlx128 [VD], [RA0], [RB]

Encoding

lvlx — form X

• Opcode word: 0x7c00040e
• Primary opcode (bits 0–5): 31
• Extended opcode: 519
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lvlx128 — form VX128_1

• Opcode word: 0x10000403
• Primary opcode (bits 0–5): 4
• Extended opcode: 1027
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
RA0	lvlx: read; lvlx128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lvlx: read; lvlx128: read	Source GPR.
VD	lvlx: write; lvlx128: write	Destination vector register.

Register Effects

lvlx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

lvlx128

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lvlx

• Canary XML: tools/ppc-instructions.xml — search for mnem="lvlx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:216
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:140
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:930

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lvlx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_lvlx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:208) ──
int InstrEmit_lvlx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                    uint32_t ra, uint32_t rb) {
  Value* ea = CalculateEA_0(f, ra, rb);

  Value* val = f.LoadVectorLeft(ea);
  f.StoreVR(vd, val);
  return 0;
}

lvlx128

• Canary XML: tools/ppc-instructions.xml — search for mnem="lvlx128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:219
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:141
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:535

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lvlx128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_lvlx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:208) ──
int InstrEmit_lvlx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                    uint32_t ra, uint32_t rb) {
  Value* ea = CalculateEA_0(f, ra, rb);

  Value* val = f.LoadVectorLeft(ea);
  f.StoreVR(vd, val);
  return 0;
}

Special Cases & Edge Conditions

• Load-left half of an unaligned vector. lvlx reads (16 - (EA mod 16)) bytes starting at the exact EA and places them in the left (high-address-byte → low-lane) of the destination vector; the remaining lanes on the right are zero-filled. Combine with lvrx at EA + 15 to assemble a full unaligned vector across an alignment boundary.
• Companion idiom. lvlx VD, RA, RB ; lvrx Vtemp, RA, RB ; vor VD, VD, Vtemp produces the unaligned 16 bytes at EA regardless of alignment. This was the canonical unaligned-vector-read recipe before lvsl/vperm shuffles became the more common idiom.
• No alignment masking. Unlike lvx, the EA is not rounded down. EA mod 16 controls how the data is shifted into the destination.
• RA0 semantics. RA = 0 selects literal zero.
• Microsoft Xbox 360 specific. lvlx and lvrx are not in the standard Altivec specification — they are part of Microsoft's VMX128 / Cell BE-style extension, defined in PowerPC Cell and later VMX. The Xbox 360 Xenon supports them, and Canary implements them (its comment: "in Cell docs only").
• Implementation in Canary. Canary emits its LoadVectorLeft op: the x64 sequence reads the 16-byte aligned block containing EA, shuffles the bytes from EA onward into the left of VD and zero-fills the right side.
• VMX128 sibling (lvlx128). Same semantics; different operand encoding (7-bit register field, addressing v0..v127).
• lvlxl is the LRU-hint variant. Same data behaviour, hint ignored under emulation.

Related Instructions

• lvrx, lvrx128 — load-right partner; combine to read unaligned 16 bytes.
• lvlxl, lvlxl128 — LRU-hint variants.
• lvx, lvx128 — aligned load (the EA-masking sibling).
• stvlx, stvrx — symmetric unaligned stores.

IBM Reference

• AIX 7.3 — lvlx (Load Vector Left Indexed)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for VMX128 details.