Sylpheed/tools/ppc-manual/memory/lvrx.md

lvrx — Load Vector Right Indexed

Category: Memory · Form: X · Opcode: 0x7c00044e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lvrx	lvrx	—	Load Vector Right Indexed
lvrx128	lvrx128	—	Load Vector Right Indexed 128

Syntax

lvrx [VD], [RA0], [RB]
lvrx128 [VD], [RA0], [RB]

Encoding

lvrx — form X

• Opcode word: 0x7c00044e
• Primary opcode (bits 0–5): 31
• Extended opcode: 551
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lvrx128 — form VX128_1

• Opcode word: 0x10000443
• Primary opcode (bits 0–5): 4
• Extended opcode: 1091
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
RA0	lvrx: read; lvrx128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lvrx: read; lvrx128: read	Source GPR.
VD	lvrx: write; lvrx128: write	Destination vector register.

Register Effects

lvrx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

lvrx128

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lvrx

• Canary XML: tools/ppc-instructions.xml — search for mnem="lvrx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:241
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:144
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:937

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lvrx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_lvrx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:229) ──
int InstrEmit_lvrx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                    uint32_t ra, uint32_t rb) {
  // NOTE: if eb == 0 (so 16b aligned) then no data is loaded. This is important
  // as often times memcpy's will use this to handle the remaining <=16b of a
  // buffer, which sometimes may be nothing and hang off the end of the valid
  // page area. We still need to zero the resulting register, though.
  Value* ea = CalculateEA_0(f, ra, rb);

  Value* val = f.LoadVectorRight(ea);
  f.StoreVR(vd, val);
  return 0;
}

lvrx128

• Canary XML: tools/ppc-instructions.xml — search for mnem="lvrx128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:244
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:145
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:536

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lvrx128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_lvrx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:229) ──
int InstrEmit_lvrx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                    uint32_t ra, uint32_t rb) {
  // NOTE: if eb == 0 (so 16b aligned) then no data is loaded. This is important
  // as often times memcpy's will use this to handle the remaining <=16b of a
  // buffer, which sometimes may be nothing and hang off the end of the valid
  // page area. We still need to zero the resulting register, though.
  Value* ea = CalculateEA_0(f, ra, rb);

  Value* val = f.LoadVectorRight(ea);
  f.StoreVR(vd, val);
  return 0;
}

Special Cases & Edge Conditions

• Load-right half of an unaligned vector. lvrx reads (EA mod 16) bytes at the addresses just below EA & ~0xF (i.e., the bytes from the previous aligned line that fall on the right side of the unaligned vector) and places them in the right (low-address-byte → high-lane) of the destination; the left lanes are zero-filled.
• Standard pair-mate of lvlx. The recipe lvlx VD, RA, RB ; lvrx Vtmp, RA, (RB+16) ; vor VD, VD, Vtmp (or some alignment-aware variant) reconstructs the unaligned 16 bytes spanning the boundary at EA.
• Right vs. left semantics. "Right" refers to lower-numbered (high-significance) lanes after rotation, not in any byte-address sense — see PowerISA Cell BE addenda for the exact bit-position formulas.
• No alignment masking. Like lvlx, the exact EA is used; the value EA mod 16 controls how data is rotated.
• RA0 semantics. RA = 0 selects literal zero.
• Implementation in Canary. Canary emits its LoadVectorRight op: when EA is 16-byte aligned the x64 sequence returns zero without reading memory; otherwise it shuffles the bytes before EA in the aligned block into the right of VD and zero-fills the left side.
• Microsoft Xbox 360 specific. Part of VMX128 / Cell BE, not in baseline Altivec.
• VMX128 sibling (lvrx128). Identical semantics; alternative operand encoding.
• lvrxl is the LRU-hint variant. Same data; cache hint ignored under emulation.

Related Instructions

• lvlx, lvlx128 — load-left partner.
• lvrxl, lvrxl128 — LRU-hint variants.
• lvx, lvx128 — aligned vector load.
• stvlx, stvrx — symmetric unaligned stores.

IBM Reference

• AIX 7.3 — lvrx (Load Vector Right Indexed)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for VMX128 unaligned-vector idioms.