Sylpheed/tools/ppc-manual/memory/stvrx.md

stvrx — Store Vector Right Indexed

Category: Memory · Form: X · Opcode: 0x7c00054e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stvrx	stvrx	—	Store Vector Right Indexed
stvrx128	stvrx128	—	Store Vector Right Indexed 128

Syntax

stvrx [VS], [RA0], [RB]
stvrx128 [VS], [RA0], [RB]

Encoding

stvrx — form X

• Opcode word: 0x7c00054e
• Primary opcode (bits 0–5): 31
• Extended opcode: 679
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stvrx128 — form VX128_1

• Opcode word: 0x10000543
• Primary opcode (bits 0–5): 4
• Extended opcode: 1347
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
VS	stvrx: read; stvrx128: read	Source vector register (alias for VD on stores).
RA0	stvrx: read; stvrx128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stvrx: read; stvrx128: read	Source GPR.

Register Effects

stvrx

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stvrx128

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stvrx

• Canary XML: tools/ppc-instructions.xml — search for mnem="stvrx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:290
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:265
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:948

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stvrx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvrx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:278) ──
int InstrEmit_stvrx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                     uint32_t ra, uint32_t rb) {
  // NOTE: if eb == 0 (so 16b aligned) then no data is loaded. This is important
  // as often times memcpy's will use this to handle the remaining <=16b of a
  // buffer, which sometimes may be nothing and hang off the end of the valid
  // page area.
  Value* ea = CalculateEA_0(f, ra, rb);

  Value* vdr = f.LoadVR(vd);
  f.StoreVectorRight(ea, vdr);
  return 0;
}

stvrx128

• Canary XML: tools/ppc-instructions.xml — search for mnem="stvrx128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:293
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:266
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:538

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stvrx128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvrx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:278) ──
int InstrEmit_stvrx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                     uint32_t ra, uint32_t rb) {
  // NOTE: if eb == 0 (so 16b aligned) then no data is loaded. This is important
  // as often times memcpy's will use this to handle the remaining <=16b of a
  // buffer, which sometimes may be nothing and hang off the end of the valid
  // page area.
  Value* ea = CalculateEA_0(f, ra, rb);

  Value* vdr = f.LoadVR(vd);
  f.StoreVectorRight(ea, vdr);
  return 0;
}

Special Cases & Edge Conditions

• Store-right half of an unaligned vector. stvrx writes (EA mod 16) bytes from the right (high-lane) half of VS to the addresses just below EA & ~0xF (the bytes from the previous aligned line that fall on the right side of the unaligned vector). The left half of VS is not stored.
• Standard pair-mate of stvlx. stvlx VS, RA, RB ; stvrx VS, RA, RB+16 (or analogous addressing) commits the 16 bytes of VS to address EA regardless of alignment. The two halves are byte-disjoint, so order is irrelevant for correctness.
• No alignment masking. Unlike stvx, the exact EA is used; EA mod 16 controls how VS splits.
• RA0 semantics. RA = 0 selects literal zero.
• Microsoft Xbox 360 specific. Part of the VMX128 / Cell BE extended set.
• Implementation in Canary. Canary emits its StoreVectorRight op, performing the unaligned partial-byte write of the right side.
• VMX128 sibling (stvrx128). Identical semantics; alternative operand encoding addressing v0..v127.
• stvrxl is the LRU-hint variant.

Related Instructions

• stvlx, stvlx128 — store-left partner.
• stvrxl, stvrxl128 — LRU-hint variants.
• stvx, stvx128 — aligned vector store.
• lvrx, lvlx — symmetric unaligned loads.

IBM Reference

• AIX 7.3 — stvrx (Store Vector Right Indexed)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for VMX128 unaligned stores.