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Sylpheed/tools/ppc-manual/memory/lvrx.md
sim f3c512f2ab docs(ppc-manual): check every xenia-rs claim against Canary's source 
The hand-written parts of the manual still described how the retired
xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of
those 490 statements is now either restated as what Canary's emitters and
x64 backend actually do (at the pinned canary_experimental commit), or
dropped where it only made sense for xenia-rs.

Checking them turned up claims that were wrong, not just outdated:

- VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr
  cannot see it); the pages said saturating ops set it stickily.
- Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1,
  vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them
  as working.
- Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not
  16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims
  and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec.
- Reservations are a 64 KiB block bitmap plus a value compare, not
  per-address tracking.

Claims that neither Canary's source nor a public spec settles are marked
unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness).

Generated regions are untouched; re-running the generator changes nothing.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 21:52:38 +02:00

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# `lvrx` — Load Vector Right Indexed
> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00044e`
<!-- GENERATED: BEGIN -->
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `lvrx` | `lvrx` | — | Load Vector Right Indexed |
| `lvrx128` | `lvrx128` | — | Load Vector Right Indexed 128 |
## Syntax
```asm
lvrx [VD], [RA0], [RB]
lvrx128 [VD], [RA0], [RB]
```
## Encoding
### `lvrx` — form `X`
- **Opcode word:** `0x7c00044e`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `551`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
### `lvrx128` — form `VX128_1`
- **Opcode word:** `0x10000443`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `1091`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `RA` | address register |
| 16–20 | `RB` | offset register |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `—` | reserved |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `RA0` | lvrx: read; lvrx128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | lvrx: read; lvrx128: read | Source GPR. |
| `VD` | lvrx: write; lvrx128: write | Destination vector register. |
## Register Effects
### `lvrx`
- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
### `lvrx128`
- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```
## C Translation Example
```c
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`lvrx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvrx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:241`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L241)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:144`](../../../crates/sylpheed-ppc/src/opcode.rs#L144)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:937`](../../../crates/sylpheed-ppc/src/decoder.rs#L937)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
```cpp
int InstrEmit_lvrx(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_lvrx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:229) ──
int InstrEmit_lvrx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
uint32_t ra, uint32_t rb) {
// NOTE: if eb == 0 (so 16b aligned) then no data is loaded. This is important
// as often times memcpy's will use this to handle the remaining <=16b of a
// buffer, which sometimes may be nothing and hang off the end of the valid
// page area. We still need to zero the resulting register, though.
Value* ea = CalculateEA_0(f, ra, rb);
Value* val = f.LoadVectorRight(ea);
f.StoreVR(vd, val);
return 0;
}
```
</details>
**`lvrx128`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvrx128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:244`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L244)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:145`](../../../crates/sylpheed-ppc/src/opcode.rs#L145)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:536`](../../../crates/sylpheed-ppc/src/decoder.rs#L536)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
```cpp
int InstrEmit_lvrx128(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_lvrx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:229) ──
int InstrEmit_lvrx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
uint32_t ra, uint32_t rb) {
// NOTE: if eb == 0 (so 16b aligned) then no data is loaded. This is important
// as often times memcpy's will use this to handle the remaining <=16b of a
// buffer, which sometimes may be nothing and hang off the end of the valid
// page area. We still need to zero the resulting register, though.
Value* ea = CalculateEA_0(f, ra, rb);
Value* val = f.LoadVectorRight(ea);
f.StoreVR(vd, val);
return 0;
}
```
</details>
<!-- GENERATED: END -->
## Special Cases & Edge Conditions
- **Load-right half of an unaligned vector.** `lvrx` reads `(EA mod 16)` bytes at the addresses *just below* `EA & ~0xF` (i.e., the bytes from the previous aligned line that fall on the right side of the unaligned vector) and places them in the **right** (low-address-byte → high-lane) of the destination; the left lanes are zero-filled.
- **Standard pair-mate of [`lvlx`](lvlx.md).** The recipe `lvlx VD, RA, RB ; lvrx Vtmp, RA, (RB+16) ; vor VD, VD, Vtmp` (or some alignment-aware variant) reconstructs the unaligned 16 bytes spanning the boundary at `EA`.
- **Right vs. left semantics.** "Right" refers to lower-numbered (high-significance) lanes after rotation, not in any byte-address sense — see PowerISA Cell BE addenda for the exact bit-position formulas.
- **No alignment masking.** Like `lvlx`, the exact `EA` is used; the value `EA mod 16` controls how data is rotated.
- **`RA0` semantics.** `RA = 0` selects literal zero.
- **Implementation in Canary.** Canary emits its `LoadVectorRight` op: when `EA` is 16-byte aligned the x64 sequence returns zero without reading memory; otherwise it shuffles the bytes before `EA` in the aligned block into the right of `VD` and zero-fills the left side.
- **Microsoft Xbox 360 specific.** Part of VMX128 / Cell BE, not in baseline Altivec.
- **VMX128 sibling (`lvrx128`).** Identical semantics; alternative operand encoding.
- **`lvrxl` is the LRU-hint variant.** Same data; cache hint ignored under emulation.
## Related Instructions
- [`lvlx`](lvlx.md), [`lvlx128`](lvlx.md) — load-left partner.
- [`lvrxl`](lvrxl.md), [`lvrxl128`](lvrxl.md) — LRU-hint variants.
- [`lvx`](lvx.md), [`lvx128`](lvx.md) — aligned vector load.
- [`stvlx`](stvlx.md), [`stvrx`](stvrx.md) — symmetric unaligned stores.
## IBM Reference
- [AIX 7.3 — `lvrx` (Load Vector Right Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lvrx-load-vector-right-indexed-instruction)
- `PowerISA v2.07B Book I` "Vector Facility"; Microsoft Xbox 360 XDK for VMX128 unaligned-vector idioms.
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