Sylpheed/tools/ppc-manual/memory/stvehx.md

stvehx — Store Vector Element Half Word Indexed

Category: Memory · Form: X · Opcode: 0x7c00014e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stvehx	stvehx	—	Store Vector Element Half Word Indexed

Syntax

stvehx [VS], [RA0], [RB]

Encoding

stvehx — form X

• Opcode word: 0x7c00014e
• Primary opcode (bits 0–5): 31
• Extended opcode: 167
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
VS	stvehx: read	Source vector register (alias for VD on stores).
RA0	stvehx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stvehx: read	Source GPR.

Register Effects

stvehx

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stvehx

• Canary XML: tools/ppc-instructions.xml — search for mnem="stvehx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:160
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:258
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:899

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stvehx(PPCHIRBuilder& f, const InstrData& i) {
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  ea = f.And(ea, f.LoadConstantUint64(~0x1ull));
  Value* el =
      f.Shr(f.And(f.Truncate(ea, INT8_TYPE), f.LoadConstantUint8(0xF)), 1);
  Value* v = f.Extract(f.LoadVR(i.X.RT), el, INT16_TYPE);
  f.Store(ea, f.ByteSwap(v));
  return 0;
}

Special Cases & Edge Conditions

• Single half-word element store. Architecturally stvehx writes exactly two bytes from half-word lane (EA mod 16) >> 1 of VS to address EA & ~1 (low bit forced to half-aligned). Other lanes are unaffected, and bytes outside the 2-byte window are unaffected.
• Two-byte write in Canary. Canary rounds EA down to even and stores just element (EA & 0xF) >> 1 (byte-swapped) — the architectural 2-byte store, leaving the rest of the line alone.
• EA forced half-aligned. Hardware drops the low bit; so does Canary (EA & ~1), which stores element (EA & 0xF) >> 1.
• RA0 semantics. RA = 0 selects literal zero.
• No update form, no VMX128 sibling. No stvehux; no stvehx128.
• Big-endian half within the lane. The byte at the lower address is the most-significant byte of the half-word lane.
• Common idiom. Pair with vsplth to broadcast then store one half; rare in compiled code (compilers prefer sth).

Related Instructions

• stvebx, stvewx — single byte / word element stores.
• stvx, stvxl — full 16-byte aligned vector stores.
• stvlx, stvrx — store-left / store-right unaligned ops.
• lvehx — symmetric single-half load.

IBM Reference

• AIX 7.3 — stvehx (Store Vector Element Half Word Indexed)
• PowerISA v2.07B Book I "Vector Facility" § "Vector Load and Store".