Sylpheed/tools/ppc-manual/vmx/vcmpeqfp.md

vcmpeqfp — Vector Compare Equal-to Floating Point

Category: VMX (Altivec) · Form: VC · Opcode: 0x100000c6

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcmpeqfp	vcmpeqfp	—	Vector Compare Equal-to Floating Point
vcmpeqfp.	vcmpeqfp	Rc=1	Vector Compare Equal-to Floating Point
vcmpeqfp128	vcmpeqfp128	—	Vector128 Compare Equal-to Floating Point
vcmpeqfp128.	vcmpeqfp128	Rc=1	Vector128 Compare Equal-to Floating Point

Syntax

vcmpeqfp[Rc] [VD], [VA], [VB]
vcmpeqfp128[Rc] [VD], [VA], [VB]

Encoding

vcmpeqfp — form VC

• Opcode word: 0x100000c6
• Primary opcode (bits 0–5): 4
• Extended opcode: 198
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21	Rc	record-form flag (updates CR6)
22–31	XO	extended opcode (10 bits)

vcmpeqfp128 — form VX128_R

• Opcode word: 0x18000000
• Primary opcode (bits 0–5): 6
• Extended opcode: 0
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22–25	XO	extended opcode (compare)
26	VA128h	source A middle bit
27	Rc	record-form flag (updates CR6)
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vcmpeqfp: read; vcmpeqfp128: read	Source A vector register.
VB	vcmpeqfp: read; vcmpeqfp128: read	Source B vector register.
VD	vcmpeqfp: write; vcmpeqfp128: write	Destination vector register.
CR	vcmpeqfp: write (conditional); vcmpeqfp128: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

vcmpeqfp

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): CR

vcmpeqfp128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): CR

Status-Register Effects

• vcmpeqfp: CR6 ← [all-true, 0, all-false, 0] when Rc=1.
• vcmpeqfp128: CR6 ← [all-true, 0, all-false, 0] when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcmpeqfp

• Canary XML: tools/ppc-instructions.xml — search for mnem="vcmpeqfp"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:623
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:323
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:675

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vcmpeqfp(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vcmpxxfp_(f, i, vcmpxxfp_eq, i.VXR.VD, i.VXR.VA, i.VXR.VB,
                             i.VXR.Rc);
}

vcmpeqfp128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vcmpeqfp128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:627
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:324
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:796

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vcmpeqfp128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vcmpxxfp_(f, i, vcmpxxfp_eq, VX128_R_VD128, VX128_R_VA128,
                             VX128_R_VB128, i.VX128_R.Rc);
}

Special Cases & Edge Conditions

• Per-lane mask: all-ones / all-zero. For each of the four word lanes, VD[i] = (VA[i] == VB[i]) ? 0xFFFFFFFF : 0. Lane 0 is the most-significant word.
• NaN handling is IEEE-754: never equal. NaN == anything is false (including NaN == NaN), so the lane stays zero. This is the standard quiet-compare behaviour — no exception, no sticky flag.
• Sign of zero ignored. +0 == -0 per IEEE-754, so the lane is set to all-ones.
• VSCR[NJ] — denormals. With NJ = 1 (Xenon default), denormal inputs are flushed to ±0 before the comparison; ±denormal == ±0 then compares as true. This is one of the few VMX float ops where the NJ flag changes program-visible mask values.
• CR6 update when Rc=1 (vcmpeqfp.). CR6 = [lt = all-true, gt = 0, eq = all-false, so = 0]; Canary's UpdateCR6 packs exactly that. Use bc 12,24 for "all-equal" branches and bc 4,26 for "any-equal".
• Compose with vsel. Mask drives vsel to pick between two source vectors per lane. Or combine masks with vand / vor / vandc to express conjunctions.
• No VSCR[SAT], no XER changes, no traps — even on signaling NaNs (Altivec's quiet-compare semantics).
• VMX128 sibling (vcmpeqfp128). Identical semantics with the extended 128-register encoding; Canary routes both opcodes to one body (InstrEmit_vcmpxxfp_).

Related Instructions

• vcmpgtfp, vcmpgefp — element-wise > and >= for floats.
• vcmpbfp — IEEE bounds check (±VB).
• vcmpequw — same shape, integer compare.
• vsel, vand, vandc, vxor — mask consumers.
• vminfp, vmaxfp — direct min / max without comparing.

IBM Reference

• AIX 7.3 — vcmpeqfp (Vector Compare Equal-to Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Compares