Sylpheed/tools/ppc-manual/alu/eieio.md

eieio — Enforce In-Order Execution of I/O

Category: Integer ALU · Form: X · Opcode: 0x7c0006ac

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
eieio	eieio	—	Enforce In-Order Execution of I/O

Syntax

eieio

Encoding

eieio — form X

• Opcode word: 0x7c0006ac
• Primary opcode (bits 0–5): 31
• Extended opcode: 854
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description

Register Effects

eieio

• Reads (always): none
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

enforce in-order execution of I/O

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

eieio

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="eieio"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:749
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:23
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:844
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1691-1693

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::sync | PpcOpcode::eieio | PpcOpcode::isync => {
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Memory-ordering barrier for caching-inhibited / guarded storage. eieio ensures all preceding loads/stores to caching-inhibited or guarded memory complete before any subsequent such accesses begin. It is weaker than sync: it does not order cacheable storage and does not flush the store queue.
• No register or CR effects. Every operand field is unused; assemblers emit the canonical 0x7c0006ac word.
• Used at MMIO boundaries. Driver code touching device registers (e.g. the GPU command processor on Xenon) typically pairs writes with eieio to enforce write ordering at the bus.
• Xenia-rs is a no-op. The interpreter trivially advances PC (interpreter.rs:1267). Because xenia-rs is a single-threaded interpreter targeting userland Xbox 360 binaries — which never see real MMIO — this is correct: the host's natural program order suffices.
• Categorised under ALU here, but operationally it's a memory ordering primitive (xenia-canary places it in ppc_emit_memory.cc). Disassembly tools may bin it differently.
• Distinct from sync and isync. All three share xenia's no-op arm in interpreter.rs:1266; on real hardware they have very different semantics and latencies.

Related Instructions

• sync — heavy memory barrier (orders all storage).
• isync — instruction-fetch barrier; refetches and re-executes after the boundary.
• lwsync — lighter weight than sync; not in this page set.

IBM Reference

• AIX 7.3 — eieio (Enforce In-Order Execution of I/O)