10dc260f0c
CONSOLIDATION.md Phase 6. Both lived untracked in the project root -- on one
disk, backed up by nothing.
tools/ppc-manual/ 393 files, 3.7 MB. 455 instructions, 350 family pages,
598 mnemonics resolvable through index.json, plus the
generator that produced them.
tools/run-canary.sh the oracle launcher.
🔴 THE LAUNCHER WAS BROKEN IN TWO WAYS AND IS REWRITTEN, not copied:
* it pointed at `xenia-rs/sylpheed.iso`, a SYMLINK. Wine cannot resolve one
and says "path invalid", which reads as a corrupt image rather than a path
problem -- it has cost a session before. It now points at the real file and
warns if handed a symlink.
* it hardcoded one machine's absolute paths, and named `xenia-rs`, which this
consolidation retires. Now derived from the script's own location, with
SYLPH_CANARY_BIN / SYLPH_ISO overrides and a check that each exists.
The standing constraints are in its header where someone will read them: one
emulator at a time, Canary runs MUTED, and never judge a crash or a hang from
a Bash-launched run -- a SIGKILL that looked like the binary was the editor's
process supervisor.
⚠️ The manual's GENERATOR reads the xenia-rs source tree, which is going away.
Its decoder now lives here as crates/sylpheed-ppc, so the generator must be
repointed before it is run again. Recorded in the README rather than left for
someone to discover; the manual's content is checked in and regenerates from
nothing implicitly.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
4.3 KiB
4.3 KiB
isync — Instruction Synchronize
Category: Integer ALU · Form: XL · Opcode:
0x4c00012c
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
isync |
isync |
— | Instruction Synchronize |
Syntax
isync
Encoding
isync — form XL
- Opcode word:
0x4c00012c - Primary opcode (bits 0–5):
19 - Extended opcode:
150 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (19) |
| 6–10 | BT/BO |
target / branch options |
| 11–15 | BA/BI |
source A / CR bit to test |
| 16–20 | BB |
source B |
| 21–30 | XO |
extended opcode (10 bits) |
| 31 | LK |
link flag |
Operands
| Field | Role | Description |
|---|
Register Effects
isync
- Reads (always): none
- Reads (conditional): none
- Writes (always): none
- Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
instruction-stream synchronisation — discards speculative state.
C Translation Example
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
isync
- xenia-canary XML:
tools/ppc-instructions.xml— search formnem="isync" - xenia-canary emit:
src/xenia/cpu/ppc/ppc_emit_memory.cc:759 - xenia-rs opcode:
crates/xenia-cpu/src/opcode.rs:32 - xenia-rs decoder:
crates/xenia-cpu/src/decoder.rs:714 - xenia-rs interpreter:
crates/xenia-cpu/src/interpreter.rs:1691-1693
xenia-rs interpreter body (frozen snapshot)
PpcOpcode::sync | PpcOpcode::eieio | PpcOpcode::isync => {
ctx.pc += 4;
}
Special Cases & Edge Conditions
- Instruction-fetch barrier. Discards any speculatively fetched/decoded instructions and forces all subsequent ones to be re-fetched after preceding instructions complete. Required after self-modifying code, JIT-emitted code, and after MMU/page-table changes.
- Stronger than
syncfor instruction stream, weaker for memory stream —isyncdoes not order stores against later loads. It only forces a fetch refresh. - Common idiom:
dcbf/icbi/sync/isync— flush data cache, invalidate instruction cache, drain memory, refetch — used by JITs and self-modifying loaders. - No operands. Encoded as a fixed-form
XLinstruction; assemblers always emit0x4c00012c. - Xenia-rs is a no-op.
interpreter.rs:1267handlessync/eieio/isynctogether. Because xenia interprets in straight-line program order without any speculative instruction cache, no barrier behaviour is needed for correctness. - Privilege level: user. Unlike most cache management ops,
isyncis unprivileged and frequently appears in userland trampolines.
Related Instructions
sync— heavy memory barrier.eieio— I/O ordering for caching-inhibited storage.icbi,dcbf,dcbst— cache management ops (outside this page set) usually paired withisync.