Sylpheed/tools/ppc-manual/alu/rldicrx.md

rldicrx — Rotate Left Doubleword Immediate then Clear Right

Category: Integer ALU · Form: MD · Opcode: 0x78000004

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rldicr	rldicrx	—	Rotate Left Doubleword Immediate then Clear Right
rldicr.	rldicrx	Rc=1	Rotate Left Doubleword Immediate then Clear Right

Syntax

rldicr[Rc] [RA], [RS], [SH], [ME]

Encoding

rldicrx — form MD

• Opcode word: 0x78000004
• Primary opcode (bits 0–5): 30
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (30)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	sh	shift amount low 5 bits
21–26	mb/me	6-bit mask field (swapped halves)
27–29	XO	extended opcode
30	sh5	shift amount high bit
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rldicrx: read	Source GPR (alias for RD in some stores).
SH	rldicrx: read	Shift amount.
ME	rldicrx: read	Mask end bit.
RA	rldicrx: write	Source GPR (r0–r31).
CR	rldicrx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rldicrx

• Reads (always): RS, SH, ME
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rldicrx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rldicrx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="rldicrx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:957
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:61
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:729
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:772-781

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::rldicrx => {
            let rs = ctx.gpr[instr.rs()];
            let sh = instr.sh64();
            let me = instr.mb_md();
            let rotated = rs.rotate_left(sh);
            let mask = rld_mask_right(me);
            ctx.gpr[instr.ra()] = rotated & mask;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← ROTL64(RS, SH) & MASK(0, ME). Rotate left by SH, then clear bits ME+1..63.
• Common simplified mnemonics:
  • sldi RA, RS, n ≡ rldicr RA, RS, n, 63-n — logical left shift by n.
  • clrrdi RA, RS, n ≡ rldicr RA, RS, 0, 63-n — clear low n bits.
  • extldi RA, RS, n, b ≡ rldicr RA, RS, b, n-1 — extract n bits from position b left-aligned.
• SH is 6 bits, immediate. Same instr.sh64() decode as the rest of the family.
• ME is 6 bits, split-encoded. Xenia stores it via instr.mb() — the field shares the slot with MB from sister instructions; the operation just interprets it as the right edge.
• Rc=1 CR0 is correctly 64-bit. Uses as i64 directly (interpreter.rs:561).
• No XER effect.
• Heavily emitted by 64-bit code generators for left-shift-and-clear sequences. Recognising the simplified mnemonics aids disassembly.

Related Instructions

• rldiclx — clear-left counterpart (MASK(MB, 63)).
• rldicx — clear both ends.
• rldcrx — register-shift version.
• rldimix — insert under mask.
• rlwinmx — 32-bit cousin.
• sldi, clrrdi, extldi (simplified mnemonics).

IBM Reference

• AIX 7.3 — rldicr (Rotate Left Doubleword Immediate then Clear Right)