Sylpheed/tools/ppc-manual/alu/rldicx.md

rldicx — Rotate Left Doubleword Immediate then Clear

Category: Integer ALU · Form: MD · Opcode: 0x78000008

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rldic	rldicx	—	Rotate Left Doubleword Immediate then Clear
rldic.	rldicx	Rc=1	Rotate Left Doubleword Immediate then Clear

Syntax

rldic[Rc] [RA], [RS], [SH], [MB]

Encoding

rldicx — form MD

• Opcode word: 0x78000008
• Primary opcode (bits 0–5): 30
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (30)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	sh	shift amount low 5 bits
21–26	mb/me	6-bit mask field (swapped halves)
27–29	XO	extended opcode
30	sh5	shift amount high bit
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rldicx: read	Source GPR (alias for RD in some stores).
SH	rldicx: read	Shift amount.
MB	rldicx: read	Mask begin bit.
RA	rldicx: write	Source GPR (r0–r31).
CR	rldicx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rldicx

• Reads (always): RS, SH, MB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rldicx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rldicx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="rldicx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:906
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:61
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:730
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:782-791

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::rldicx => {
            let rs = ctx.gpr[instr.rs()];
            let sh = instr.sh64();
            let mb = instr.mb_md();
            let rotated = rs.rotate_left(sh);
            let mask = rld_mask_left(mb) & rld_mask_right(63 - sh);
            ctx.gpr[instr.ra()] = rotated & mask;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← ROTL64(RS, SH) & MASK(MB, 63 - SH). Rotate RS left by SH bits, then mask off both ends: clear bits 0..MB-1 and clear bits 64-SH..63. This is the "clear at both edges" variant — useful for inserting a field into an otherwise-zero register.
• SH is a 6-bit immediate spanning bits 16–20 plus bit 30 of the instruction word. Xenia uses the helper instr.sh64() (interpreter.rs:566) to assemble the 6 bits.
• MB is also 6-bit, split-encoded like the rest of the rld* family: (instr.mb() << 1) | ((raw >> 1) & 1).
• Mask is computed as MASK_LEFT(MB) AND MASK_RIGHT(63 - SH). This produces the equivalent of "left-shift RS by SH then clear high bits above bit MB" — a common pattern when MB ≤ 63 - SH.
• Equivalent to a logical shift when MB = 0. rldic RA, RS, SH, 0 ≡ sldi RA, RS, SH (an alias the assembler may prefer).
• Rc=1 CR0 is correctly 64-bit. interpreter.rs:571 uses as i64 directly.
• No XER effect.

Related Instructions

• rldiclx, rldicrx — clear-only-one-side variants.
• rldclx, rldcrx — register-shift forms.
• rldimix — insert under mask.
• rlwinmx — 32-bit cousin.
• sldi (simplified) — rldic RA, RS, n, 0; assemblers prefer this for plain logical left shifts.

IBM Reference

• AIX 7.3 — rldic (Rotate Left Doubleword Immediate then Clear)