Sylpheed/tools/ppc-manual/memory/lfd.md

lfd — Load Floating-Point Double

Category: Memory · Form: D · Opcode: 0xc8000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lfd	lfd	—	Load Floating-Point Double
lfdu	lfdu	—	Load Floating-Point Double with Update
lfdux	lfdux	—	Load Floating-Point Double with Update Indexed
lfdx	lfdx	—	Load Floating-Point Double Indexed

Syntax

lfd [FD], [d]([RA0])
lfdu [FD], [d]([RA])
lfdux [FD], [RA], [RB]
lfdx [FD], [RA0], [RB]

Encoding

lfd — form D

• Opcode word: 0xc8000000
• Primary opcode (bits 0–5): 50
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

lfdu — form D

• Opcode word: 0xcc000000
• Primary opcode (bits 0–5): 51
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

lfdux — form X

• Opcode word: 0x7c0004ee
• Primary opcode (bits 0–5): 31
• Extended opcode: 631
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lfdx — form X

• Opcode word: 0x7c0004ae
• Primary opcode (bits 0–5): 31
• Extended opcode: 599
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lfd: read; lfdx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
d	lfd: read; lfdu: read	16-bit signed displacement (d) added to the base address register.
FD	lfd: write; lfdu: write; lfdux: write; lfdx: write	Destination floating-point register.
RA	lfdu: read; lfdu: write; lfdux: read; lfdux: write	Source GPR (r0–r31).
RB	lfdux: read; lfdx: read	Source GPR.

Register Effects

lfd

• Reads (always): RA0, d
• Reads (conditional): none
• Writes (always): FD
• Writes (conditional): none

lfdu

• Reads (always): RA, d
• Reads (conditional): none
• Writes (always): FD, RA
• Writes (conditional): none

lfdux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): FD, RA
• Writes (conditional): none

lfdx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): FD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(d)
FRT <- MEM(EA, 8)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lfd

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lfd"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:912
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:38
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:373
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1152-1157

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lfd => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(instr.d() as i64 as u64) as u32;
            ctx.fpr[instr.rd()] = mem.read_f64(ea);
            ctx.pc += 4;
        }

lfdu

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lfdu"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:925
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:38
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:374
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1176-1181

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lfdu => {
            let ea = ctx.gpr[instr.ra()].wrapping_add(instr.d() as i64 as u64) as u32;
            ctx.fpr[instr.rd()] = mem.read_f64(ea);
            ctx.gpr[instr.ra()] = ea as u64;
            ctx.pc += 4;
        }

lfdux

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lfdux"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:936
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:38
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:827
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1182-1187

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lfdux => {
            let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
            ctx.fpr[instr.rd()] = mem.read_f64(ea);
            ctx.gpr[instr.ra()] = ea as u64;
            ctx.pc += 4;
        }

lfdx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lfdx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:947
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:38
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:826
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1158-1163

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lfdx => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            ctx.fpr[instr.rd()] = mem.read_f64(ea);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Bit-exact double load. Reads 8 bytes and places them directly into FRT as IEEE-754 binary64. No format conversion is performed (contrast lfs, which expands single→double).
• No FPSCR side effects. lfd cannot raise IEEE exceptions: it neither rounds nor inspects the value. A signalling NaN read this way stays a signalling NaN until it is consumed by an arithmetic op.
• RA0 semantics. In the non-update forms (lfd, lfdx), RA = 0 selects literal zero — lfd FT, 0(0) loads from absolute address 0. Update forms lfdu / lfdux invoke RA = 0 and RA = RT (here RA is GPR; RT is FPR, so the latter cannot collide) as invalid forms when RA = 0.
• Alignment. Xenon tolerates unaligned 8-byte FP loads; PowerISA technically permits implementations to raise alignment exceptions for FP loads, so portable code uses 8-byte aligned addresses.
• Big-endian read. Bytes are interpreted big-endian: byte at EA is bits 0–7 of the IEEE pattern (sign + part of exponent), byte at EA+7 is bits 56–63 of the mantissa. mem.read_f64 in xenia handles the host-side byte-swap.
• MSR[FP] required. Like all FP-register accesses, lfd requires the FP unit be enabled (MSR[FP]=1). Otherwise a Floating-Point Unavailable interrupt is raised. Xenia assumes FP is always enabled in user code.
• Pair with stfd. Store-double is the symmetric counterpart.

Related Instructions

• lfs — single-precision load with format conversion to double.
• stfd, stfdu, stfdx, stfdux — corresponding stores.
• stfiwx — store-FP-as-integer-word (the asymmetric oddity in the FP load/store family).
• ld — integer doubleword load (same width, GPR target).

IBM Reference

• AIX 7.3 — lfd (Load Floating-Point Double)
• AIX 7.3 — lfdu / lfdx / lfdux