Sylpheed/tools/ppc-manual/memory/lfs.md

lfs — Load Floating-Point Single

Category: Memory · Form: D · Opcode: 0xc0000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lfs	lfs	—	Load Floating-Point Single
lfsu	lfsu	—	Load Floating-Point Single with Update
lfsux	lfsux	—	Load Floating-Point Single with Update Indexed
lfsx	lfsx	—	Load Floating-Point Single Indexed

Syntax

lfs [FD], [d]([RA0])
lfsu [FD], [d]([RA])
lfsux [FD], [RA], [RB]
lfsx [FD], [RA0], [RB]

Encoding

lfs — form D

• Opcode word: 0xc0000000
• Primary opcode (bits 0–5): 48
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

lfsu — form D

• Opcode word: 0xc4000000
• Primary opcode (bits 0–5): 49
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

lfsux — form X

• Opcode word: 0x7c00046e
• Primary opcode (bits 0–5): 31
• Extended opcode: 567
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lfsx — form X

• Opcode word: 0x7c00042e
• Primary opcode (bits 0–5): 31
• Extended opcode: 535
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lfs: read; lfsx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
d	lfs: read; lfsu: read	16-bit signed displacement (d) added to the base address register.
FD	lfs: write; lfsu: write; lfsux: write; lfsx: write	Destination floating-point register.
RA	lfsu: read; lfsu: write; lfsux: read; lfsux: write	Source GPR (r0–r31).
RB	lfsux: read; lfsx: read	Source GPR.

Register Effects

lfs

• Reads (always): RA0, d
• Reads (conditional): none
• Writes (always): FD
• Writes (conditional): none

lfsu

• Reads (always): RA, d
• Reads (conditional): none
• Writes (always): FD, RA
• Writes (conditional): none

lfsux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): FD, RA
• Writes (conditional): none

lfsx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): FD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(d)
FRT <- DoubleFromSingle(MEM(EA, 4))

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lfs

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lfs"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:960
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:38
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:371
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1140-1145

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lfs => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(instr.d() as i64 as u64) as u32;
            ctx.fpr[instr.rd()] = mem.read_f32(ea) as f64;
            ctx.pc += 4;
        }

lfsu

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lfsu"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:974
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:38
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:372
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1164-1169

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lfsu => {
            let ea = ctx.gpr[instr.ra()].wrapping_add(instr.d() as i64 as u64) as u32;
            ctx.fpr[instr.rd()] = mem.read_f32(ea) as f64;
            ctx.gpr[instr.ra()] = ea as u64;
            ctx.pc += 4;
        }

lfsux

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lfsux"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:986
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:38
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:823
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1170-1175

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lfsux => {
            let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
            ctx.fpr[instr.rd()] = mem.read_f32(ea) as f64;
            ctx.gpr[instr.ra()] = ea as u64;
            ctx.pc += 4;
        }

lfsx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lfsx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:998
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:38
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:819
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1146-1151

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lfsx => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            ctx.fpr[instr.rd()] = mem.read_f32(ea) as f64;
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Single → double in-register. Reads 4 bytes as IEEE binary32, then exactly converts to binary64 (every binary32 has a representation in binary64). The result occupies all 64 bits of the FPR; subsequent FP arithmetic operates in double regardless of the value's origin.
• No FPSCR side effects. The single→double widening is exact, so lfs cannot raise inexact, overflow, underflow, or invalid. A signalling NaN passes through unchanged into the FPR — it will signal at the next FP arithmetic instruction.
• Subnormals. A binary32 subnormal expands to a binary64 normal — lfs quietly normalises. There is no "FPSCR[NI] non-IEEE mode" subnormal-to-zero behaviour applied at this stage on Xenon (NI affects arithmetic, not loads).
• RA0 semantics. In lfs / lfsx, RA = 0 selects literal zero. Update forms lfsu / lfsux are invalid with RA = 0.
• Alignment. Xenon tolerates unaligned 4-byte loads; PowerISA permits implementations to raise alignment exceptions for FP loads on cache-inhibited storage.
• Big-endian read. Bytes EA..EA+3 form the binary32 pattern, sign bit at EA[7]. Xenia's mem.read_f32 handles host byte-swap.
• MSR[FP] required. Disabled FP unit raises Floating-Point Unavailable.
• Pair with stfs. Store-single performs the inverse double→single rounding (which can raise FPSCR exceptions because that direction may be inexact).

Related Instructions

• lfd — double-precision load (no format conversion).
• stfs, stfsu, stfsx, stfsux — corresponding stores; these can round.
• stfiwx — store-FP-as-integer-word.
• lwz — integer word load (same width, GPR target).

IBM Reference

• AIX 7.3 — lfs (Load Floating-Point Single)
• AIX 7.3 — lfsu / lfsx / lfsux