Sylpheed/tools/ppc-manual/alu/addis.md

addis — Add Immediate Shifted

Category: Integer ALU · Form: D · Opcode: 0x3c000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
addis	addis	—	Add Immediate Shifted

Syntax

addis [RD], [RA0], [SIMM]

Encoding

addis — form D

• Opcode word: 0x3c000000
• Primary opcode (bits 0–5): 15
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RA0	addis: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
SIMM	addis: read	16-bit signed immediate. Sign-extended to 64 bits before use.
RD	addis: write	Destination GPR.

Register Effects

addis

• Reads (always): RA0, SIMM
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

if RA = 0 then RT <- EXTS(SIMM) << 16
else             RT <- (RA) + (EXTS(SIMM) << 16)

C Translation Example

/* addis RT, RA, SIMM  — RA=0 means literal 0                     */
uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
r[insn.RT] = base + ((uint64_t)(int64_t)(int16_t)insn.SIMM << 16);

Implementation References

addis

• Canary XML: tools/ppc-instructions.xml — search for mnem="addis"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:138
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:13
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:454

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_addis(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   RT <- EXTS(SI) || i16.0
  // else
  //   RT <- (RA) + EXTS(SI) || i16.0
  Value* si = f.LoadConstantInt64(XEEXTS16(i.D.DS) << 16);
  Value* v = si;
  if (i.D.RA) {
    v = f.Add(f.LoadGPR(i.D.RA), si);
  }
  f.StoreGPR(i.D.RT, v);
  return 0;
}

Special Cases & Edge Conditions

• RA0 semantics. When the RA field encodes 0, the operand is the literal 64-bit zero, not r0. This makes addis RT, 0, hi16 the canonical "load high half" idiom. To use r0's actual value as a base, copy it via mr first or use a different opcode.
• Immediate is sign-extended then shifted left 16. So addis r3, 0, 0x8000 writes 0xFFFFFFFF80000000, not 0x000000008000_0000. The 32-bit sign extension surprise is the most common bug in hand-written PPC assembly.
• Forms the high half of a 32-bit immediate. The classic lis rT, hi; ori rT, rT, lo (or lis/addi) sequence builds a full 32-bit constant. lis rT, val is a simplified mnemonic for addis rT, 0, val.
• No XER[CA], no XER[OV], no Rc. This instruction has no status side-effects whatsoever. Use addic or addcx if a carry is required.
• 64-bit RA operand. The shift-and-add is 64-bit on the Xenon; the immediate's sign-extension fills the high 48 bits. So addis r3, r4, -1 adds 0xFFFFFFFFFFFF0000 to a 64-bit r4.
• No overflow detection. lis r3, 0x7FFF; addis r3, r3, 0x7FFF happily wraps without comment.

Related Instructions

• addi — D-form add immediate, no shift; same RA0 rule.
• addic, addicx — immediate adds that also write XER[CA].
• oris, ori — pair with addis/lis to build 32-bit constants without affecting CR or XER.
• addx, addcx — XO-form register adds.
• lis (simplified) — assembler shorthand for addis RT, 0, value.

IBM Reference

• AIX 7.3 — addis (Add Immediate Shifted)
• AIX 7.3 — lis (Load Immediate Shifted, simplified mnemonic)