Sylpheed/tools/ppc-manual/memory/lhbrx.md

lhbrx — Load Half Word Byte-Reverse Indexed

Category: Memory · Form: X · Opcode: 0x7c00062c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lhbrx	lhbrx	—	Load Half Word Byte-Reverse Indexed

Syntax

lhbrx [RD], [RA0], [RB]

Encoding

lhbrx — form X

• Opcode word: 0x7c00062c
• Primary opcode (bits 0–5): 31
• Extended opcode: 790
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lhbrx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lhbrx: read	Source GPR.
RD	lhbrx: write	Destination GPR.

Register Effects

lhbrx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lhbrx

• Canary XML: tools/ppc-instructions.xml — search for mnem="lhbrx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:628
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:126
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:954

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lhbrx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // RT <- i48.0 || bswap(MEM(EA, 2))
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  Value* rt = f.ZeroExtend(f.Load(ea, INT16_TYPE), INT64_TYPE);
  StoreEA(f, i.X.RT, rt);
  return 0;
}

Special Cases & Edge Conditions

• Reads little-endian half. Loads 2 bytes and swaps them: byte at EA becomes the low 8 bits of RT[16:23], byte at EA+1 becomes the upper 8 bits. The xenia snapshot does mem.read_u16(ea).swap_bytes(). Effective for parsing little-endian on-disk or network half-word fields.
• Zero-extension to 64 bits. Result occupies the full 64-bit GPR; high 48 bits are zero. There is no sign-extending byte-reverse load (lhbrx + extsh if you need one).
• X-form only — no update form. Like all byte-reverse loads, only the indexed form exists. EA = (RA|0) + RB. Pointer-bumping requires a separate addi.
• RA0 semantics. When RA = 0, base is the literal zero — lhbrx RT, 0, RB reads at exact RB.
• Alignment. Hardware tolerates unaligned half-word reads. Xenon may take alignment exceptions on cache-inhibited storage.
• Common in stream parsers. PNG, ZIP, BMP, WAV chunk decoders use lhbrx to read little-endian length fields.

Related Instructions

• lwbrx, ldbrx — wider byte-reverse loads.
• sthbrx — store-half byte-reverse counterpart.
• lhz, lhzx — non-reversing zero-extending half loads.
• lha — non-reversing sign-extending half load.

IBM Reference

• AIX 7.3 — lhbrx (Load Half Byte-Reverse Indexed)
• PowerISA v2.07B Book II § "Byte-Reverse Storage Access".