Sylpheed/tools/ppc-manual/memory/lhz.md

lhz — Load Half Word and Zero

Category: Memory · Form: D · Opcode: 0xa0000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lhz	lhz	—	Load Half Word and Zero
lhzu	lhzu	—	Load Half Word and Zero with Update
lhzux	lhzux	—	Load Half Word and Zero with Update Indexed
lhzx	lhzx	—	Load Half Word and Zero Indexed

Syntax

lhz [RD], [d]([RA0])
lhzu [RD], [d]([RA])
lhzux [RD], [RA], [RB]
lhzx [RD], [RA0], [RB]

Encoding

lhz — form D

• Opcode word: 0xa0000000
• Primary opcode (bits 0–5): 40
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

lhzu — form D

• Opcode word: 0xa4000000
• Primary opcode (bits 0–5): 41
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

lhzux — form X

• Opcode word: 0x7c00026e
• Primary opcode (bits 0–5): 31
• Extended opcode: 311
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lhzx — form X

• Opcode word: 0x7c00022e
• Primary opcode (bits 0–5): 31
• Extended opcode: 279
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lhz: read; lhzx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
d	lhz: read; lhzu: read	16-bit signed displacement (d) added to the base address register.
RD	lhz: write; lhzu: write; lhzux: write; lhzx: write	Destination GPR.
RA	lhzu: read; lhzu: write; lhzux: read; lhzux: write	Source GPR (r0–r31).
RB	lhzux: read; lhzx: read	Source GPR.

Register Effects

lhz

• Reads (always): RA0, d
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

lhzu

• Reads (always): RA, d
• Reads (conditional): none
• Writes (always): RD, RA
• Writes (conditional): none

lhzux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD, RA
• Writes (conditional): none

lhzx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(d)
RT <- ZEXT16_to_64(MEM(EA, 2))

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lhz

• Canary XML: tools/ppc-instructions.xml — search for mnem="lhz"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:186
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:127
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:478

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lhz(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + EXTS(D)
  // RT <- i48.0 || MEM(EA, 2)
  Value* b;
  if (i.D.RA == 0) {
    b = f.LoadZeroInt64();
  } else {
    b = f.LoadGPR(i.D.RA);
  }

  Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
  Value* rt =
      f.ZeroExtend(f.ByteSwap(f.LoadOffset(b, offset, INT16_TYPE)), INT64_TYPE);
  f.StoreGPR(i.D.RT, rt);
  return 0;
}

lhzu

• Canary XML: tools/ppc-instructions.xml — search for mnem="lhzu"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:207
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:128
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:479

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lhzu(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + EXTS(D)
  // RT <- i48.0 || MEM(EA, 2)
  // RA <- EA
  Value* ra = f.LoadGPR(i.D.RA);
  Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
  Value* rt = f.ZeroExtend(f.ByteSwap(f.LoadOffset(ra, offset, INT16_TYPE)),
                           INT64_TYPE);
  f.StoreGPR(i.D.RT, rt);
  StoreEA(f, i.D.RA, f.Add(ra, offset));
  return 0;
}

lhzux

• Canary XML: tools/ppc-instructions.xml — search for mnem="lhzux"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:220
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:129
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:912

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lhzux(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + (RB)
  // RT <- i48.0 || MEM(EA, 2)
  // RA <- EA
  Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
  Value* rt = f.ZeroExtend(f.ByteSwap(f.Load(ea, INT16_TYPE)), INT64_TYPE);
  f.StoreGPR(i.X.RT, rt);
  StoreEA(f, i.X.RA, ea);
  return 0;
}

lhzx

• Canary XML: tools/ppc-instructions.xml — search for mnem="lhzx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:231
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:130
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:910

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lhzx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // RT <- i48.0 || MEM(EA, 2)
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  Value* rt = f.ZeroExtend(f.ByteSwap(f.Load(ea, INT16_TYPE)), INT64_TYPE);
  f.StoreGPR(i.X.RT, rt);
  return 0;
}

Special Cases & Edge Conditions

• Big-endian read, zero-extension. Reads 2 bytes big-endian, treats them as an unsigned 16-bit integer, zero-extends to 64 bits. The high 48 bits of RT become zero. Compare with lha, which sign-extends.
• RA0 (non-update forms). RA = 0 in lhz / lhzx selects literal zero for absolute-address access. Update forms lhzu / lhzux invoke RA = 0 and RA = RT as invalid forms.
• Update-form ordering. Xenia computes EA, performs the load, then writes RA ← EA. If RA == RT (an invalid form per IBM), the load result is overwritten by EA immediately.
• No alignment requirement. Xenon executes unaligned half-word loads without faulting. MEM(EA, 2) reads the two consecutive bytes at EA.
• Common as Unicode codepoint loader. Xbox 360 system strings are UTF-16; lhz is the canonical load for a single 16-bit codepoint.
• Use lhz rather than lbz × 2 + shift. One fused instruction is faster and lets the load-store unit handle alignment.
• Indexed variant operand order. lhzx RT, RA, RB — RA is the base (with RA0 semantics), RB is the offset.

Related Instructions

• lha, lhau, lhax, lhaux — sign-extending counterparts.
• lbz, lwz, ld — narrower / wider zero-extending loads.
• lhbrx — byte-reversed half load (little-endian half).
• sth, sthu, sthx, sthux — corresponding stores.

IBM Reference

• AIX 7.3 — lhz (Load Half and Zero)
• AIX 7.3 — lhzu / lhzx / lhzux