Sylpheed/tools/ppc-manual/memory/lha.md

lha — Load Half Word Algebraic

Category: Memory · Form: D · Opcode: 0xa8000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lha	lha	—	Load Half Word Algebraic
lhau	lhau	—	Load Half Word Algebraic with Update
lhaux	lhaux	—	Load Half Word Algebraic with Update Indexed
lhax	lhax	—	Load Half Word Algebraic Indexed

Syntax

lha [RD], [d]([RA0])
lhau [RD], [d]([RA])
lhaux [RD], [RA], [RB]
lhax [RD], [RA0], [RB]

Encoding

lha — form D

• Opcode word: 0xa8000000
• Primary opcode (bits 0–5): 42
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

lhau — form D

• Opcode word: 0xac000000
• Primary opcode (bits 0–5): 43
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

lhaux — form X

• Opcode word: 0x7c0002ee
• Primary opcode (bits 0–5): 31
• Extended opcode: 375
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lhax — form X

• Opcode word: 0x7c0002ae
• Primary opcode (bits 0–5): 31
• Extended opcode: 343
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lha: read; lhax: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
d	lha: read; lhau: read	16-bit signed displacement (d) added to the base address register.
RD	lha: write; lhau: write; lhaux: write; lhax: write	Destination GPR.
RA	lhau: read; lhau: write; lhaux: read; lhaux: write	Source GPR (r0–r31).
RB	lhaux: read; lhax: read	Source GPR.

Register Effects

lha

• Reads (always): RA0, d
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

lhau

• Reads (always): RA, d
• Reads (conditional): none
• Writes (always): RD, RA
• Writes (conditional): none

lhaux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD, RA
• Writes (conditional): none

lhax

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(d)
RT <- SEXT16_to_64(MEM(EA, 2))

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lha

• Canary XML: tools/ppc-instructions.xml — search for mnem="lha"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:128
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:122
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:480

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lha(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + EXTS(D)
  // RT <- EXTS(MEM(EA, 2))
  Value* b;
  if (i.D.RA == 0) {
    b = f.LoadZeroInt64();
  } else {
    b = f.LoadGPR(i.D.RA);
  }

  Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
  Value* rt =
      f.SignExtend(f.ByteSwap(f.LoadOffset(b, offset, INT16_TYPE)), INT64_TYPE);
  f.StoreGPR(i.D.RT, rt);
  return 0;
}

lhau

• Canary XML: tools/ppc-instructions.xml — search for mnem="lhau"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:149
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:123
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:481

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lhau(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + EXTS(D)
  // RT <- EXTS(MEM(EA, 2))
  // RA <- EA
  Value* ra = f.LoadGPR(i.D.RA);
  Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
  Value* rt = f.SignExtend(f.ByteSwap(f.LoadOffset(ra, offset, INT16_TYPE)),
                           INT64_TYPE);
  f.StoreGPR(i.D.RT, rt);
  StoreEA(f, i.D.RA, f.Add(ra, offset));
  return 0;
}

lhaux

• Canary XML: tools/ppc-instructions.xml — search for mnem="lhaux"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:162
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:124
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:920

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lhaux(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + (RB)
  // RT <- EXTS(MEM(EA, 2))
  // RA <- EA
  Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
  Value* rt = f.SignExtend(f.ByteSwap(f.Load(ea, INT16_TYPE)), INT64_TYPE);
  f.StoreGPR(i.X.RT, rt);
  StoreEA(f, i.X.RA, ea);
  return 0;
}

lhax

• Canary XML: tools/ppc-instructions.xml — search for mnem="lhax"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:173
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:125
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:916

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lhax(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // RT <- EXTS(MEM(EA, 2))
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  Value* rt = f.SignExtend(f.ByteSwap(f.Load(ea, INT16_TYPE)), INT64_TYPE);
  f.StoreGPR(i.X.RT, rt);
  return 0;
}

Special Cases & Edge Conditions

• Sign-extending half-word load. Reads 2 bytes big-endian, treats them as a signed 16-bit integer, sign-extends to 64 bits. Compare with lhz, which zero-extends. Xenia's snapshot does the cast chain u16 -> i16 -> i64 -> u64 to obtain the canonical sign-extended bit pattern.
• Big-endian read. Byte at EA is the most-significant 8 bits of the half; byte at EA+1 is the least-significant. On little-endian hosts mem.read_u16 returns the big-endian word in host-native form already.
• RA0 (non-update forms). RA = 0 in lha and lhax selects literal zero — useful for absolute-address access patterns.
• Update-form invalid forms. lhau / lhaux invoke RA = 0 and RA = RT as invalid forms; xenia performs the load before writing back RA ← EA, so an RA = RT collision silently destroys the loaded value.
• No alignment requirement. Xenon executes unaligned half-word loads without a fault.
• Common in audio / graphics code. lha is the standard load for signed 16-bit PCM samples and signed 16-bit packed vertex deltas.
• Use lha rather than lhz + extsh. Both produce the same result, but lha is one fused instruction and the compiler will pick it whenever the source type is int16_t / short.

Related Instructions

• lhz, lhzu, lhzx, lhzux — zero-extending counterparts.
• lwa, lwax, lwaux — sign-extending word loads (32→64).
• lbz — byte load (no sign-extending byte load exists; use lbz + extsb).
• lhbrx — byte-reversed half-word load (zero-extending).
• sth, sthu, sthx, sthux — corresponding stores.

IBM Reference

• AIX 7.3 — lha (Load Half Algebraic)
• AIX 7.3 — lhau / lhax / lhaux