Sylpheed/tools/ppc-manual/memory/stswi.md

stswi — Store String Word Immediate

Category: Memory · Form: X · Opcode: 0x7c0005aa

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stswi	stswi	—	Store String Word Immediate

Syntax

(no disassembly template)

Encoding

stswi — form X

• Opcode word: 0x7c0005aa
• Primary opcode (bits 0–5): 31
• Extended opcode: 725
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description

Register Effects

stswi

• Reads (always): none
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stswi

• Canary XML: tools/ppc-instructions.xml — search for mnem="stswi"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:737
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:254
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:950

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stswi(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}

Special Cases & Edge Conditions

• Byte-granular bulk store. Symmetric counterpart of lswi. Reads the low 32 bits of RS, RS+1, …, takes the top byte of each (then the next, etc.) and writes successive bytes at EA. The byte count NB is in the RB field of the encoding (1..31), with NB = 0 meaning "32 bytes".
• Register wraparound at r31 → r0. Xenia's snapshot increments rs = (rs + 1) % 32. After r31 the source becomes r0, then r1, etc. Rare in practice; AIX flags overlapping register / address ranges as invalid.
• Big-endian byte ordering inside each register. Writes the most-significant byte first: mem.write_u8(ea, (val >> 24) as u8), then bits 16–23, etc. Matches the byte order produced by lswi, so a lswi/stswi pair round-trips a buffer.
• Last partial register. When NB is not a multiple of 4, the final source register has its trailing low bytes ignored — only the leading bytes that fit in the byte budget are written.
• RA0 semantics. RA = 0 selects literal zero. stswi is not an update form; RA is not modified.
• Alignment. Architecture allows arbitrary alignment; cache-inhibited storage may raise alignment exceptions on hardware.
• Vanishingly rare in compiled code. Compilers don't emit stswi. Hand-written memcpy cores may.

Related Instructions

• lswi — symmetric load.
• stswx — register-supplied byte-count variant.
• stmw — word-granular bulk store.
• stw, stb — scalar stores compilers actually emit.

IBM Reference

• AIX 7.3 — stswi (Store String Word Immediate)
• PowerISA v2.07B Book II § "Load and Store String".