Sylpheed/tools/ppc-manual/memory/stb.md

stb — Store Byte

Category: Memory · Form: D · Opcode: 0x98000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stb	stb	—	Store Byte
stbu	stbu	—	Store Byte with Update
stbux	stbux	—	Store Byte with Update Indexed
stbx	stbx	—	Store Byte Indexed

Syntax

stb [RS], [d]([RA0])
stbu [RS], [d]([RA])
stbux [RS], [RA], [RB]
stbx [RS], [RA0], [RB]

Encoding

stb — form D

• Opcode word: 0x98000000
• Primary opcode (bits 0–5): 38
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

stbu — form D

• Opcode word: 0x9c000000
• Primary opcode (bits 0–5): 39
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

stbux — form X

• Opcode word: 0x7c0001ee
• Primary opcode (bits 0–5): 31
• Extended opcode: 247
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stbx — form X

• Opcode word: 0x7c0001ae
• Primary opcode (bits 0–5): 31
• Extended opcode: 215
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	stb: read; stbu: read; stbux: read; stbx: read	Source GPR (alias for RD in some stores).
RA0	stb: read; stbx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
d	stb: read; stbu: read	16-bit signed displacement (d) added to the base address register.
RA	stbu: read; stbu: write; stbux: read; stbux: write	Source GPR (r0–r31).
RB	stbux: read; stbx: read	Source GPR.

Register Effects

stb

• Reads (always): RS, RA0, d
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stbu

• Reads (always): RS, RA, d
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

stbux

• Reads (always): RS, RA, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

stbx

• Reads (always): RS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(d)
MEM(EA, 1) <- (RS)[56:63]

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stb

• Canary XML: tools/ppc-instructions.xml — search for mnem="stb"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:404
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:225
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:476

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stb(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + EXTS(D)
  // MEM(EA, 1) <- (RS)[56:63]
  Value* b;
  if (i.D.RA == 0) {
    b = f.LoadZeroInt64();
  } else {
    b = f.LoadGPR(i.D.RA);
  }

  Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
  f.StoreOffset(b, offset, f.Truncate(f.LoadGPR(i.D.RT), INT8_TYPE));
  return 0;
}

stbu

• Canary XML: tools/ppc-instructions.xml — search for mnem="stbu"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:423
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:226
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:477

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stbu(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + EXTS(D)
  // MEM(EA, 1) <- (RS)[56:63]
  // RA <- EA
  Value* ea = CalculateEA_i(f, i.D.RA, XEEXTS16(i.D.DS));
  f.Store(ea, f.Truncate(f.LoadGPR(i.D.RT), INT8_TYPE));
  StoreEA(f, i.D.RA, ea);
  return 0;
}

stbux

• Canary XML: tools/ppc-instructions.xml — search for mnem="stbux"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:433
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:227
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:908

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stbux(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + (RB)
  // MEM(EA, 1) <- (RS)[56:63]
  // RA <- EA
  Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
  f.Store(ea, f.Truncate(f.LoadGPR(i.X.RT), INT8_TYPE));
  StoreEA(f, i.X.RA, ea);
  return 0;
}

stbx

• Canary XML: tools/ppc-instructions.xml — search for mnem="stbx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:443
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:228
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:905

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stbx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // MEM(EA, 1) <- (RS)[56:63]
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  f.Store(ea, f.Truncate(f.LoadGPR(i.X.RT), INT8_TYPE));
  return 0;
}

Special Cases & Edge Conditions

• Single-byte write. Writes the low 8 bits of RS ((RS)[56:63] in IBM bit-numbering, equivalently RS & 0xFF) at EA. The xenia snapshot does mem.write_u8(ea, ctx.gpr[instr.rs()] as u8), which casts the GPR's low byte directly.
• No endian concerns. A single byte has no endianness — the byte at EA is the byte you wrote.
• RA0 (non-update forms). RA = 0 in stb and stbx selects literal zero as base — useful for absolute writes. Update forms stbu / stbux invoke RA = 0 as an invalid form (no RA = RT collision since the source is RS, not RT).
• Update-form post-write. stbu / stbux write the computed EA back to RA after the store. The order is store-then-update; if RA = RS the store is unaffected (the store reads RS first), but the new RA value reflects EA, not the original RS.
• No alignment requirement. Byte stores are intrinsically aligned. Xenon never raises alignment exceptions for byte writes.
• Common in string and packed-bool code. Compilers emit stb for char * writes, packed boolean array updates, and small enum stores.
• Cache effects. A stb to a cold cache line triggers a cache-line read-allocate (load the whole line, modify one byte, mark dirty). When writing many bytes sequentially, prefer one stw or stvx, or pre-clear the line with dcbz128.

Related Instructions

• sth, stw, std — wider stores (half / word / doubleword).
• lbz — corresponding load (no lba exists).
• stmw, stswi, stswx — multi-word / string stores for bulk transfer.
• stwbrx, sthbrx — byte-reversed wider stores (no byte-equivalent needed).

IBM Reference

• AIX 7.3 — stb (Store Byte)
• AIX 7.3 — stbu (Store Byte with Update)