Sylpheed/tools/ppc-manual/memory/stswx.md

stswx — Store String Word Indexed

Category: Memory · Form: X · Opcode: 0x7c00052a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stswx	stswx	—	Store String Word Indexed

Syntax

(no disassembly template)

Encoding

stswx — form X

• Opcode word: 0x7c00052a
• Primary opcode (bits 0–5): 31
• Extended opcode: 661
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description

Register Effects

stswx

• Reads (always): none
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stswx

• Canary XML: tools/ppc-instructions.xml — search for mnem="stswx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:742
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:255
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:945

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stswx(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}

Special Cases & Edge Conditions

• Byte count from XER[25..31]. Unlike stswi, the byte count NB (0..127) is read from XER[25..31]. The xenia snapshot does let nb = (ctx.xer() & 0x7F) as u32;. NB = 0 means literally zero bytes — the instruction becomes a no-op.
• Register packing identical to stswi. Bytes are pulled from successive GPRs, four bytes per register, big-endian within each register, with wraparound r31 → r0. The final partial register's unused trailing bytes are not written.
• RA0 semantics. RA = 0 selects literal zero. The instruction has no update form — RA is not modified.
• Invalid forms. AIX flags as invalid the cases where the byte-stream wraps through RA or RB while reading the source registers; xenia performs writes regardless.
• Big-endian byte ordering inside each register. Writes most-significant byte of each source GPR's low word first.
• Used for non-multiple-of-4 copies. Together with lswx, gives a way to store a runtime-determined byte count without per-byte loops. Compilers don't emit it.
• Alignment. Architecture allows arbitrary alignment; cache-inhibited storage may raise alignment exceptions on hardware.
• No CR / FPSCR effects.

Related Instructions

• lswx — symmetric load.
• stswi — sibling with byte count encoded as RB field (immediate-style).
• stmw — word-granular bulk store (no byte tail handling).
• stw, stb — scalar stores.

IBM Reference

• AIX 7.3 — stswx (Store String Word Indexed)
• PowerISA v2.07B Book II § "Load and Store String" for invalid-form rules and XER interaction.