Sylpheed/tools/ppc-manual/memory/stvewx.md

stvewx — Store Vector Element Word Indexed

Category: Memory · Form: X · Opcode: 0x7c00018e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stvewx	stvewx	—	Store Vector Element Word Indexed
stvewx128	stvewx128	—	Store Vector Element Word Indexed 128

Syntax

stvewx [VS], [RA0], [RB]
stvewx128 [VS], [RA0], [RB]

Encoding

stvewx — form X

• Opcode word: 0x7c00018e
• Primary opcode (bits 0–5): 31
• Extended opcode: 199
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stvewx128 — form VX128_1

• Opcode word: 0x10000183
• Primary opcode (bits 0–5): 4
• Extended opcode: 387
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
VS	stvewx: read; stvewx128: read	Source vector register (alias for VD on stores).
RA0	stvewx: read; stvewx128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stvewx: read; stvewx128: read	Source GPR.

Register Effects

stvewx

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stvewx128

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stvewx

• Canary XML: tools/ppc-instructions.xml — search for mnem="stvewx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:180
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:259
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:903

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stvewx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvewx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:170) ──
int InstrEmit_stvewx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                      uint32_t ra, uint32_t rb) {
  Value* ea = CalculateEA_0(f, ra, rb);
  ea = f.And(ea, f.LoadConstantUint64(~0x3ull));
  Value* el =
      f.Shr(f.And(f.Truncate(ea, INT8_TYPE), f.LoadConstantUint8(0xF)), 2);
  Value* v = f.Extract(f.LoadVR(vd), el, INT32_TYPE);
  f.Store(ea, f.ByteSwap(v));
  return 0;
}

stvewx128

• Canary XML: tools/ppc-instructions.xml — search for mnem="stvewx128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:183
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:260
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:531

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stvewx128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvewx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:170) ──
int InstrEmit_stvewx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                      uint32_t ra, uint32_t rb) {
  Value* ea = CalculateEA_0(f, ra, rb);
  ea = f.And(ea, f.LoadConstantUint64(~0x3ull));
  Value* el =
      f.Shr(f.And(f.Truncate(ea, INT8_TYPE), f.LoadConstantUint8(0xF)), 2);
  Value* v = f.Extract(f.LoadVR(vd), el, INT32_TYPE);
  f.Store(ea, f.ByteSwap(v));
  return 0;
}

Special Cases & Edge Conditions

• Single word element store. Architecturally stvewx writes exactly four bytes from word lane (EA mod 16) >> 2 of VS to address EA & ~3 (low two bits forced to word-aligned). Other lanes are unaffected, and bytes outside the 4-byte window are unaffected.
• Xenia simplification — full 16-byte write. Both stvewx and stvewx128 snapshots write the full 16 bytes of the source vector at ea & ~0xF. This overwrites 12 bytes that hardware would have left alone.
• EA forced word-aligned. Hardware drops the low two bits; xenia's snapshots drop the low four.
• RA0 semantics. RA = 0 selects literal zero.
• No update form. No stvewux.
• VMX128 sibling (stvewx128). Identical semantics; alternative operand encoding addressing v0..v127 via the split-field 7-bit register index.
• Big-endian word within the lane. The byte at the lower address is the most-significant byte.
• Common idiom. Pair with vspltw to broadcast a 32-bit FP/integer value, then stvewx to commit one lane. Less common than stw from a GPR.

Related Instructions

• stvebx, stvehx — single byte / half element stores.
• stvx, stvx128, stvxl — full 16-byte aligned vector stores.
• stvlx, stvrx — store-left / store-right unaligned ops.
• lvewx, lvewx128 — symmetric single-word loads.

IBM Reference

• AIX 7.3 — stvewx (Store Vector Element Word Indexed)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for stvewx128.