Sylpheed/tools/ppc-manual/alu/extswx.md

extswx — Extend Sign Word

Category: Integer ALU · Form: X · Opcode: 0x7c0007b4

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
extsw	extswx	—	Extend Sign Word
extsw.	extswx	Rc=1	Extend Sign Word

Syntax

extsw[Rc] [RA], [RS]

Encoding

extswx — form X

• Opcode word: 0x7c0007b4
• Primary opcode (bits 0–5): 31
• Extended opcode: 986
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	extswx: read	Source GPR (alias for RD in some stores).
RA	extswx: write	Source GPR (r0–r31).
CR	extswx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

extswx

• Reads (always): RS
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• extswx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- EXTS_32_to_64((RS)[32:63])

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

extswx

• Canary XML: tools/ppc-instructions.xml — search for mnem="extswx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:740
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:62
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:967

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_extswx(PPCHIRBuilder& f, const InstrData& i) {
  // s <- (RS)[32]
  // RA[32:63] <- (RS)[32:63]
  // RA[0:31] <- i32.s
  Value* rt = f.LoadGPR(i.X.RT);
  rt = f.SignExtend(f.Truncate(rt, INT32_TYPE), INT64_TYPE);
  f.StoreGPR(i.X.RA, rt);
  if (i.X.Rc) {
    f.UpdateCR(0, rt);
  }
  return 0;
}

Special Cases & Edge Conditions

• Sign-extends the low 32 bits of RS to 64 bits. Bit 32 (sign bit of the word) is replicated through bits 0–31 of RA.
• Used heavily in 32-to-64-bit promotion. Most Xbox 360 ABI parameters are 32-bit; promoting a 32-bit int to a 64-bit GPR requires this instruction. Many functions emit it on entry to canonicalise their argument registers.
• Rc=1 CR0 update is correctly 64-bit. interpreter.rs:399 uses as i64 (no truncation) — one of the few xenia-rs sites where the spec width is honoured. The signed compare in CR0 reflects the full sign-extended value.
• Operand convention is the X-form one (RA destination, RS source).
• No XER side effects.
• RB field unused.
• Aliasing is fine. extsw r3, r3 is the canonical "sign-extend in place" idiom.
• Distinct from srawi RA, RS, 31, which produces the sign mask (-1 if negative else 0) rather than the sign-extended value.

Related Instructions

• extsbx, extshx — narrower sign extensions.
• srawix — to derive a sign mask instead.
• rldiclx — to zero-extend the low 32 bits.
• lwa / lwax (memory ops) — combined load-and-sign-extend; lives outside this set.

IBM Reference

• AIX 7.3 — extsw (Extend Sign Word)