Sylpheed/tools/ppc-manual/alu/srawix.md

srawix — Shift Right Algebraic Word Immediate

Category: Integer ALU · Form: X · Opcode: 0x7c000670

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
srawi	srawix	—	Shift Right Algebraic Word Immediate
srawi.	srawix	Rc=1	Shift Right Algebraic Word Immediate

Syntax

srawi[Rc] [RA], [RS], [SH]

Encoding

srawix — form X

• Opcode word: 0x7c000670
• Primary opcode (bits 0–5): 31
• Extended opcode: 824
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	srawix: read	Source GPR (alias for RD in some stores).
SH	srawix: read	Shift amount.
RA	srawix: write	Source GPR (r0–r31).
CR	srawix: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
CA	srawix: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.

Register Effects

srawix

• Reads (always): RS, SH
• Reads (conditional): none
• Writes (always): RA, CA
• Writes (conditional): CR

Status-Register Effects

• srawix: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

RA <- ((RS)[32:63] >>a SH) sign-extended
CA <- (RS[32] signed) && any_low_bit_shifted_out

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

srawix

• Canary XML: tools/ppc-instructions.xml — search for mnem="srawix"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:1291
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:220
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:958

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_srawix(PPCHIRBuilder& f, const InstrData& i) {
  // n <- SH
  // r <- ROTL32((RS)[32:63], 64-n)
  // m <- MASK(n+32, 63)
  // s <- (RS)[32]
  // RA <- r&m | (i64.s)&¬m
  // CA <- s & ((r&¬m)[32:63]≠0)
  // if n == 0: rA <- sign_extend(rS), XER[CA] = 0
  // if n >= 32: rA <- 64 sign bits of rS, XER[CA] = sign bit of lo_32(rS)
  Value* v = f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE);
  Value* ca;
  if (!i.X.RB) {
    // No shift, just a fancy sign extend and CA clearer.
    v = f.SignExtend(v, INT64_TYPE);
    ca = f.LoadZeroInt8();
  } else {
    // CA is set if any bits are shifted out of the right and if the result
    // is negative.
    uint32_t mask = (uint32_t)XEMASK(64 - i.X.RB, 63);

    if (mask == 1) {
      ca = f.And(f.CompareSLT(v, f.LoadConstantInt32(0)),
                 f.Truncate(v, INT8_TYPE));

    } else {
      ca = f.And(f.CompareSLT(v, f.LoadConstantInt32(0)),
                 f.IsTrue(f.And(v, f.LoadConstantUint32(mask))));
    }

    v = f.Sha(v, (int8_t)i.X.RB), v = f.SignExtend(v, INT64_TYPE);
  }
  f.StoreCA(ca);
  f.StoreGPR(i.X.RA, v);
  if (i.X.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← ((i32)RS >> SH) sign-extended with XER[CA] set when RS is negative AND any low bit was shifted out.
• SH is 5 bits (immediate, range 0..31). Unlike srawx, there is no saturation case because the count cannot exceed 31. Xenia reads it via instr.sh().
• SH = 0 sign-extends RS[32:63] to 64 bits and clears CA. This is not a no-op when RS's high 32 bits differ from the sign extension of bit 32.
• Common idiom: srawi rA, rS, 31 materialises the 32-bit sign of rS as 0 or −1 — the canonical "sign mask" pattern. Often used for branchless abs or conditional negation.
• Idiom: srawi rA, rS, n; addze rA, rA — divide signed by 2^n rounding toward zero.
• Rc=1 CR0 update truncates to 32 bits in xenia-rs. interpreter.rs:457 — matches spec because the sign-extended result has consistent low/high 32-bit signs.
• No OE bit.

Related Instructions

• srawx — register-shift form.
• sradix, sradx — 64-bit arithmetic right.
• addzex — divide-rounding companion.
• extswx — srawi rA, rS, 0 is functionally a sign-extend-32-to-64 plus CA = 0 clear; extsw is preferred when CA isn't wanted.

IBM Reference

• AIX 7.3 — srawi (Shift Right Algebraic Word Immediate)