Sylpheed/tools/ppc-manual/alu/mullwx.md

mullwx — Multiply Low Word

Category: Integer ALU · Form: XO · Opcode: 0x7c0001d6

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mullw	mullwx	—	Multiply Low Word
mullwo	mullwx	OE=1	Multiply Low Word
mullw.	mullwx	Rc=1	Multiply Low Word
mullwo.	mullwx	OE=1, Rc=1	Multiply Low Word

Syntax

mullw[OE][Rc] [RD], [RA], [RB]

Encoding

mullwx — form XO

• Opcode word: 0x7c0001d6
• Primary opcode (bits 0–5): 31
• Extended opcode: 235
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	mullwx: read	Source GPR (r0–r31).
RB	mullwx: read	Source GPR.
RD	mullwx: write	Destination GPR.
CR	mullwx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
OE	mullwx: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.

Register Effects

mullwx

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): CR, OE

Status-Register Effects

• mullwx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- ((RA)[32:63]) * ((RB)[32:63])    ; signed 32×32 → 64

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mullwx

• Canary XML: tools/ppc-instructions.xml — search for mnem="mullwx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:390
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:194
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:989

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mullwx(PPCHIRBuilder& f, const InstrData& i) {
  // RT <- (RA)[32:63] × (RB)[32:63]
  if (i.XO.OE) {
    // With XER update.
    XEINSTRNOTIMPLEMENTED();
  }
  Value* v = f.Mul(
      f.SignExtend(f.Truncate(f.LoadGPR(i.XO.RA), INT32_TYPE), INT64_TYPE),
      f.SignExtend(f.Truncate(f.LoadGPR(i.XO.RB), INT32_TYPE), INT64_TYPE));
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Extended Pseudocode

prod64 <- sign_extend_32_to_64((RA)[32:63]) *s sign_extend_32_to_64((RB)[32:63])
RT <- prod64                                         ; 64-bit result
if OE then
    XER[OV] <- (prod64 ≠ sign_extend_32_to_64(prod64[32:63]))  ; set when product doesn't fit in 32 bits
    XER[SO] <- XER[SO] | XER[OV]
if Rc then
    CR0 <- signed_compare(RT, 0) || XER[SO]

Special Cases & Edge Conditions

• Inputs are the low 32 bits. mullw only looks at RA[32:63] and RB[32:63]; the high 32 bits of each source are ignored. This is a 32-bit × 32-bit → 64-bit signed multiply. For full 64-bit operands use mulldx.
• Result is sign-extended to 64 bits. The 64-bit product fits into a 64-bit GPR without loss. Subsequent 32-bit consumers see RT[32:63] (the low 32 bits of the product); use mulhwx for the signed high 32 bits or mulhwux for the unsigned high 32 bits, computed in parallel without this instruction.
• OE overflow test is 32-bit. XER[OV] is set iff the 64-bit signed product cannot be represented in 32 bits — equivalently, iff RT[32] ≠ RT[33] = … = RT[63] (sign bit disagrees with the next 32 bits). Xenia-rs does not implement this; OE on mullwo is a no-op in the interpreter.
• Xenia-rs CR0 update bug footprint. The interpreter computes CR0 from result as i32 as i64 — the low 32 bits sign-extended. For a 32×32→64 multiply the high 32 bits may be non-zero even when the low 32 bits are zero, so xenia's CR0 can differ from the spec's (which compares the full 64-bit product to zero). In practice this matters only for code that relies on mullw. to detect overflow via CR0 — extremely rare.
• Latency. On the Xenon, mullw has higher latency than add/sub; many hot inner loops avoid it by strength-reduction or shift-add chains. This is irrelevant for correctness but sometimes explains surprising instruction sequences in disassembly.

Related Instructions

• mulhwx — signed high 32 bits of the same 32×32 product.
• mulhwux — unsigned high 32 bits of a 32×32 product.
• mulli — D-form: RT ← (RA[32:63]) × SIMM (low 64 bits, signed).
• mulldx, mulhdx, mulhdux — 64-bit multiplies (low/high, signed/unsigned).
• divwx, divwux — 32-bit signed / unsigned division.

IBM Reference

• AIX 7.3 — mullw (Multiply Low Word)
• AIX 7.3 — mulli (Multiply Low Immediate)