Sylpheed/tools/ppc-manual/alu/divwux.md

divwux — Divide Word Unsigned

Category: Integer ALU · Form: XO · Opcode: 0x7c000396

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
divwu	divwux	—	Divide Word Unsigned
divwuo	divwux	OE=1	Divide Word Unsigned
divwu.	divwux	Rc=1	Divide Word Unsigned
divwuo.	divwux	OE=1, Rc=1	Divide Word Unsigned

Syntax

divwu[OE][Rc] [RD], [RA], [RB]

Encoding

divwux — form XO

• Opcode word: 0x7c000396
• Primary opcode (bits 0–5): 31
• Extended opcode: 459
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	divwux: read	Source GPR (r0–r31).
RB	divwux: read	Source GPR.
RD	divwux: write	Destination GPR.
OE	divwux: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	divwux: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

divwux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): OE, CR

Status-Register Effects

• divwux: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- ((RA)[32:63] /u (RB)[32:63]) zero-extended to 64 ; undefined if RB=0

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

divwux

• Canary XML: tools/ppc-instructions.xml — search for mnem="divwux"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:269
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:54
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:992

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_divwux(PPCHIRBuilder& f, const InstrData& i) {
  // dividend[0:31] <- (RA)[32:63]
  // divisor[0:31] <- (RB)[32:63]
  // if divisor = 0 then
  //   if OE = 1 then
  //     XER[OV] <- 1
  //   return
  // RT[32:63] <- dividend ÷ divisor
  // RT[0:31] <- undefined
  Value* divisor = f.Truncate(f.LoadGPR(i.XO.RB), INT32_TYPE);
  // TODO(benvanik): check if zero
  //                 if OE=1, set XER[OV] = 1
  //                 else skip the divide
  Value* v = f.Div(f.Truncate(f.LoadGPR(i.XO.RA), INT32_TYPE), divisor,
                   ARITHMETIC_UNSIGNED);
  v = f.ZeroExtend(v, INT64_TYPE);
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.OE) {
    // If we are OE=1 we need to clear the overflow bit.
    // e.update_xer_with_overflow(e.get_uint64(0));
    XEINSTRNOTIMPLEMENTED();
  }
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• 32-bit operands, zero-extended result. Both RA and RB are read as their low 32 bits, unsigned (as u32); the quotient is computed as u32, then zero-extended to 64 bits. The high 32 bits of RA/RB are ignored on input and the high 32 bits of RT are zero on output.
• Single undefined case. Division by zero (RB == 0); xenia-rs returns 0 (interpreter.rs:251). No INT_MIN/-1 case because the operands are unsigned.
• No trap on Xenon. Same as divdx — silent undefined result.
• OE=1 should set XER[OV] on RB == 0; xenia-rs ignores this.
• Rc=1 CR0 update. interpreter.rs:256 uses as i32 as i64 — for an unsigned 32-bit quotient stored in the low 32 bits with high zeros, this matches spec exactly; the i32 view will be negative iff the unsigned quotient ≥ 2^31. Worth flagging when comparing CR0 against zero after a large divwu.
• Truncating quotient. Floor division for non-negative integers; matches C unsigned semantics.
• Same slow non-pipelined latency as divw.

Related Instructions

• divwx — signed 32-bit divide.
• divdux, divdx — 64-bit variants.
• mullwx — pair to recover the remainder.
• cmplwi (simplified) — guard the divisor.

IBM Reference

• AIX 7.3 — divwu (Divide Word Unsigned)