Sylpheed/tools/ppc-manual/alu/rldclx.md

rldclx — Rotate Left Doubleword then Clear Left

Category: Integer ALU · Form: MDS · Opcode: 0x78000010

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rldcl	rldclx	—	Rotate Left Doubleword then Clear Left
rldcl.	rldclx	Rc=1	Rotate Left Doubleword then Clear Left

Syntax

rldcl[Rc] [RA], [RS], [RB], [MB]

Encoding

rldclx — form MDS

• Opcode word: 0x78000010
• Primary opcode (bits 0–5): 30
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (30)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	RB	source B GPR
21–26	mb/me	6-bit mask field (swapped halves)
27–30	XO	extended opcode
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rldclx: read	Source GPR (alias for RD in some stores).
RB	rldclx: read	Source GPR.
MB	rldclx: read	Mask begin bit.
RA	rldclx: write	Source GPR (r0–r31).
CR	rldclx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rldclx

• Reads (always): RS, RB, MB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rldclx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rldclx

• Canary XML: tools/ppc-instructions.xml — search for mnem="rldclx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:856
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:204
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:848

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_rldclx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- rB[58:63]
  // r <- ROTL[64](rS, n)
  // b <- mb[5] || mb[0:4]
  // m <- MASK(b, 63)
  // rA <- r & m
  Value* n = f.And(f.Truncate(f.LoadGPR(i.MDS.RB), INT8_TYPE),
                   f.LoadConstantInt8(0x3F));

  uint32_t mb = (i.MDS.MB5 << 5) | i.MDS.MB;
  uint64_t m = XEMASK(mb, 63);
  Value* v = f.LoadGPR(i.MDS.RT);

  v = f.RotateLeft(v, n);
  if (m != 0xFFFFFFFFFFFFFFFF) {
    v = f.And(v, f.LoadConstantUint64(m));
  }

  f.StoreGPR(i.MDS.RA, v);
  if (i.MDS.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← ROTL64(RS, RB[58:63]) & MASK(MB, 63). Rotate RS left by RB & 0x3F, then clear bits to the left of MB — i.e. keep bits MB..63, force bits 0..MB-1 to zero.
• Shift comes from a register. Unlike rldiclx, the rotate amount is dynamic. Only the low 6 bits of RB are used (& 0x3F); the upper 58 bits are silently ignored.
• MB is a split 6-bit field. Bit 5 of the encoded mb/me is swapped into bit position 5 (raw bit 30) — xenia decodes via (instr.mb() << 1) | ((raw >> 1) & 1) (interpreter.rs:587). This MDS form is unusual; if you write a decoder, follow this exact bit assembly.
• Mask generation. rld_mask_left(MB) is (1 << (64 - MB)) - 1 — i.e. clear bits 0..MB-1, keep bits MB..63. When MB = 0 the mask is all ones; when MB = 63 only bit 63 survives.
• Rc=1 CR0 is correctly 64-bit. interpreter.rs:592 uses as i64 directly — no truncation. The rotate-and-mask family is one of the few xenia-rs instruction groups that already does the spec-correct 64-bit CR0 compare.
• No XER effect.
• Use over rldiclx when the shift amount is computed at runtime (e.g. via cntlzd for normalisation).

Related Instructions

• rldcrx — sister: clear right instead of left.
• rldiclx, rldicrx, rldicx — immediate-shift variants.
• rldimix — rotate and mask insert.
• rlwnmx, rlwinmx — 32-bit cousins.
• sldx, srdx — preferred for plain 64-bit shifts.

IBM Reference

• AIX 7.3 — rldcl (Rotate Left Doubleword then Clear Left)