Sylpheed/tools/ppc-manual/alu/rlwnmx.md

rlwnmx — Rotate Left Word then AND with Mask

Category: Integer ALU · Form: M · Opcode: 0x5c000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rlwnm	rlwnmx	—	Rotate Left Word then AND with Mask
rlwnm.	rlwnmx	Rc=1	Rotate Left Word then AND with Mask

Syntax

rlwnm[Rc] [RA], [RS], [RB], [MB], [ME]

Encoding

rlwnmx — form M

• Opcode word: 0x5c000000
• Primary opcode (bits 0–5): 23
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	SH/RB	shift amount or source B
21–25	MB	mask begin
26–30	ME	mask end
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rlwnmx: read	Source GPR (alias for RD in some stores).
RB	rlwnmx: read	Source GPR.
MB	rlwnmx: read	Mask begin bit.
ME	rlwnmx: read	Mask end bit.
RA	rlwnmx: write	Source GPR (r0–r31).
CR	rlwnmx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rlwnmx

• Reads (always): RS, RB, MB, ME
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rlwnmx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rlwnmx

• Canary XML: tools/ppc-instructions.xml — search for mnem="rlwnmx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:1101
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:212
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:461

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_rlwnmx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- (RB)[59:63]
  // r <- ROTL32((RS)[32:63], n)
  // m <- MASK(MB+32, ME+32)
  // RA <- r & m
  Value* sh =
      f.And(f.Truncate(f.LoadGPR(i.M.SH), INT8_TYPE), f.LoadConstantInt8(0x1F));
  Value* v = f.LoadGPR(i.M.RT);
  // (x||x)
  v = f.Or(f.Shl(v, 32), f.ZeroExtend(f.Truncate(v, INT32_TYPE), INT64_TYPE));
  v = f.RotateLeft(v, sh);
  v = f.And(v, f.LoadConstantUint64(XEMASK(i.M.MB + 32, i.M.ME + 32)));
  f.StoreGPR(i.M.RA, v);
  if (i.M.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← ROTL32(RS[32:63], RB[59:63]) & MASK(MB, ME). Identical to rlwinmx except the rotate amount comes from the low 5 bits of RB. Xenia masks with & 0x1F (interpreter.rs:535).
• Use over rlwinm when the rotate amount is dynamic (e.g. computed from a cntlzw for normalisation, or read from a parameter).
• Mask is still 5+5 bits immediate — MB and ME are not register-sourced; only the shift is. This is the M-form's quirk: only one of (SH, MB, ME) is variable across the family.
• Donut masks supported. MB > ME produces a wraparound mask, same as rlwinm.
• High 32 bits of RA are zero (32-bit operation, then as u64 zero-extends).
• Rc=1 CR0 update truncates to 32 bits in xenia-rs. interpreter.rs:540 — harmless because the result already fits in 32 bits.
• No XER effect.

Related Instructions

• rlwinmx — same op, immediate shift.
• rlwimix — insert variant (no register-shift form exists for insert).
• rldclx, rldcrx — 64-bit register-shift cousins.
• slwx, srwx — straight 32-bit shifts.

IBM Reference

• AIX 7.3 — rlwnm (Rotate Left Word then AND with Mask)