Sylpheed/tools/ppc-manual/alu/slwx.md

slwx — Shift Left Word

Category: Integer ALU · Form: X · Opcode: 0x7c000030

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
slw	slwx	—	Shift Left Word
slw.	slwx	Rc=1	Shift Left Word

Syntax

slw[Rc] [RA], [RS], [RB]

Encoding

slwx — form X

• Opcode word: 0x7c000030
• Primary opcode (bits 0–5): 31
• Extended opcode: 24
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	slwx: read	Source GPR (alias for RD in some stores).
RB	slwx: read	Source GPR.
RA	slwx: write	Source GPR (r0–r31).
CR	slwx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

slwx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• slwx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

n <- (RB)[58:63]
RA <- ((RS) << n) & 0x0000_0000_FFFF_FFFF if n < 32 else 0

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

slwx

• Canary XML: tools/ppc-instructions.xml — search for mnem="slwx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:1141
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:217
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:872

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_slwx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- (RB)[59:63]
  // r <- ROTL32((RS)[32:63], n)
  // if (RB)[58] = 0 then
  //   m <- MASK(32, 63-n)
  // else
  //   m <- i64.0
  // RA <- r & m
  Value* sh =
      f.And(f.Truncate(f.LoadGPR(i.X.RB), INT8_TYPE), f.LoadConstantInt8(0x3F));
  Value* v = f.Select(f.IsTrue(f.Shr(sh, 5)), f.LoadZeroInt32(),
                      f.Shl(f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE), sh));
  v = f.ZeroExtend(v, INT64_TYPE);
  f.StoreGPR(i.X.RA, v);
  if (i.X.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• 32-bit logical left shift, zero-extended to 64. RA ← (RS[32:63] << (RB & 0x3F))[32:63] if (RB & 0x3F) < 32, else RA = 0. The high 32 bits of RA are always zero (zero-extension of the 32-bit result).
• Shift count is 6 bits, RB[58:63] — not 7 like sldx. Counts in [32, 63] produce zero. Xenia reads the full register but the explicit if sh < 32 guard in interpreter.rs:417 prevents Rust UB.
• Spec quirk worth flagging: xenia reads ctx.gpr[instr.rb()] as u32, which uses the low 32 bits of RB, not the spec's RB & 0x3F. For ordinary code these agree (counts ≤ 63), but a maliciously high RB could in principle differ. In practice this is a non-issue.
• No XER[CA] for left shifts.
• Rc=1 CR0 update truncates to 32 bits (interpreter.rs:420). Since the high 32 bits are zero, this matches spec exactly.
• No OE bit.

Related Instructions

• sldx — 64-bit logical left shift.
• srwx, srawx, srawix — 32-bit right shifts.
• rlwinmx — slwi simplified mnemonic uses this.

IBM Reference

• AIX 7.3 — slw (Shift Left Word)