Sylpheed/tools/ppc-manual/vmx/vrfip.md

# `vrfip` — Vector Round to Floating-Point Integer toward +Infinity

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000028a`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vrfip` | `vrfip` | — | Vector Round to Floating-Point Integer toward +Infinity |
| `vrfip128` | `vrfip128` | — | Vector128 Round to Floating-Point Integer toward +Infinity |

## Syntax

```asm
vrfip [VD], [VB]
vrfip128 [VD], [VB]
```

## Encoding

### `vrfip` — form `VX`

- **Opcode word:** `0x1000028a`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `650`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

### `vrfip128` — form `VX128_3`

- **Opcode word:** `0x180003b0`
- **Primary opcode (bits 0–5):** `6`
- **Extended opcode:** `944`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (6) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `IMM` | 5-bit immediate |
| 16–20 | `VB128l` | source B low 5 bits |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VB` | vrfip: read; vrfip128: read | Source B vector register. |
| `VD` | vrfip: write; vrfip128: write | Destination vector register. |

## Register Effects

### `vrfip`

- **Reads (always):** `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

### `vrfip128`

- **Reads (always):** `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vrfip`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vrfip"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1242`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1242)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:427`](../../../crates/sylpheed-ppc/src/opcode.rs#L427)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:607`](../../../crates/sylpheed-ppc/src/decoder.rs#L607)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_vrfip(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vrfip_(f, i.VX.VD, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1236) ──
int InstrEmit_vrfip_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- RndToFPInt32Ceil(VB)
  Value* v = f.Round(f.LoadVR(vb), ROUND_TO_POSITIVE_INFINITY);
  f.StoreVR(vd, v);
  return 0;
}
```
</details>

**`vrfip128`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vrfip128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1245`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1245)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:428`](../../../crates/sylpheed-ppc/src/opcode.rs#L428)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:777`](../../../crates/sylpheed-ppc/src/decoder.rs#L777)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_vrfip128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vrfip_(f, VX128_3_VD128, VX128_3_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1236) ──
int InstrEmit_vrfip_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- RndToFPInt32Ceil(VB)
  Value* v = f.Round(f.LoadVR(vb), ROUND_TO_POSITIVE_INFINITY);
  f.StoreVR(vd, v);
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Round toward plus-infinity (ceiling).** Each 32-bit float lane of `VB` is rounded up. `3.2 → 4.0`, `−3.2 → −3.0`.
- **IEEE-754 binary32 output; `VSCR[NJ]` honoured.**
- **Integer-too-big lanes are no-ops.**
- **NaN and ±∞** pass through.
- **No VSCR[SAT], no FPSCR update.**
- **Big-endian lane indexing.**
- **VMX128 sibling `vrfip128`.**

## Related Instructions

- [`vrfim`](vrfim.md) — round toward −∞ (the symmetric partner).
- [`vrfin`](vrfin.md) — round to nearest.
- [`vrfiz`](vrfiz.md) — round toward zero.
- [`vctsxs`](vctsxs.md), [`vctuxs`](vctuxs.md) — float → fixed-point integer.

## IBM Reference

- [AIX 7.3 — `vrfip` (Vector Round to Floating-Point Integer toward Plus Infinity)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vrfip-vector-round-floating-point-integer-toward-plus-infinity-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)