[x64] Fix vector mask issue and add missing tests

src/xenia/cpu/ppc/testing/instr_vsrab.s

@@ -0,0 +1,55 @@
+test_vsrab_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsrab v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vsrab_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsrab v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+
+test_vsrab_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707]
+  vsrab v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]
+
+test_vsrab_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808]
+  vsrab v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808]
+
+test_vsrab_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [09090909, 09090909, 09090909, 09090909]
+  vsrab v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [09090909, 09090909, 09090909, 09090909]
+
+test_vsrab_6:
+  #_ REGISTER_IN v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsrab v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3F3F3F3F, 3F3F3F3F, 3F3F3F3F, 3F3F3F3F]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+
+test_vsrab_7:
+  #_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsrab v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [C0C0C0C0, C0C0C0C0, C0C0C0C0, C0C0C0C0]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]

src/xenia/cpu/ppc/testing/instr_vsrah.s

@@ -1,4 +1,68 @@
 test_vsrah_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsrah v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vsrah_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vsrah v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+
+test_vsrah_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [000F000F, 000F000F, 000F000F, 000F000F]
+  vsrah v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [000F000F, 000F000F, 000F000F, 000F000F]
+
+test_vsrah_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00100010, 00100010, 00100010, 00100010]
+  vsrah v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00100010, 00100010, 00100010, 00100010]
+
+test_vsrah_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00090009, 00090009, 00090009, 00090009]
+  vsrah v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00090009, 00090009, 00090009, 00090009]
+
+test_vsrah_6:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00110011, 00110011, 00110011, 00110011]
+  vsrah v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00110011, 00110011, 00110011, 00110011]
+
+test_vsrah_7:
+  #_ REGISTER_IN v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vsrah v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3FFF3FFF, 3FFF3FFF, 3FFF3FFF, 3FFF3FFF]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+
+test_vsrah_8:
+  #_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vsrah v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [C000C000, C000C000, C000C000, C000C000]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+
+test_vsrah_9:
   #_ REGISTER_IN v3 [12345678, 87654321, 11223344, 55667788]
   #_ REGISTER_IN v4 [000D000D, 000D000D, 000D000D, 000D000D]
   vsrah v5, v3, v4

src/xenia/cpu/ppc/testing/instr_vsraw.s

@@ -0,0 +1,63 @@
+test_vsraw_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsraw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vsraw_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsraw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+
+test_vsraw_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [0000001F, 0000001F, 0000001F, 0000001F]
+  vsraw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [0000001F, 0000001F, 0000001F, 0000001F]
+
+test_vsraw_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000020, 00000020, 00000020, 00000020]
+  vsraw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000020, 00000020, 00000020, 00000020]
+
+test_vsraw_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000009, 00000009, 00000009, 00000009]
+  vsraw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000009, 00000009, 00000009, 00000009]
+
+test_vsraw_6:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000021, 00000021, 00000021, 00000021]
+  vsraw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000021, 00000021, 00000021, 00000021]
+
+test_vsraw_7:
+  #_ REGISTER_IN v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsraw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3FFFFFFF, 3FFFFFFF, 3FFFFFFF, 3FFFFFFF]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+
+test_vsraw_8:
+  #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsraw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]

src/xenia/cpu/ppc/testing/instr_vsrb.s

@@ -0,0 +1,47 @@
+test_vsrb_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsrb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vsrb_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsrb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+
+test_vsrb_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707]
+  vsrb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]
+
+test_vsrb_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808]
+  vsrb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808]
+
+test_vsrb_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [09090909, 09090909, 09090909, 09090909]
+  vsrb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_OUT v4 [09090909, 09090909, 09090909, 09090909]
+
+test_vsrb_6:
+  #_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsrb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [40404040, 40404040, 40404040, 40404040]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]

src/xenia/cpu/ppc/testing/instr_vsrh.s

@@ -1,4 +1,52 @@
 test_vsrh_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsrh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vsrh_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vsrh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+
+test_vsrh_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [000F000F, 000F000F, 000F000F, 000F000F]
+  vsrh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v4 [000F000F, 000F000F, 000F000F, 000F000F]
+
+test_vsrh_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00100010, 00100010, 00100010, 00100010]
+  vsrh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00100010, 00100010, 00100010, 00100010]
+
+test_vsrh_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00090009, 00090009, 00090009, 00090009]
+  vsrh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [007F007F, 007F007F, 007F007F, 007F007F]
+  #_ REGISTER_OUT v4 [00090009, 00090009, 00090009, 00090009]
+
+test_vsrh_6:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00110011, 00110011, 00110011, 00110011]
+  vsrh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+  #_ REGISTER_OUT v4 [00110011, 00110011, 00110011, 00110011]
+
+test_vsrh_7:
   #_ REGISTER_IN v3 [12345678, 87654321, 11223344, 55667788]
   #_ REGISTER_IN v4 [000D000D, 000D000D, 000D000D, 000D000D]
   vsrh v5, v3, v4

src/xenia/cpu/ppc/testing/instr_vsrw.s

@@ -0,0 +1,55 @@
+test_vsrw_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsrw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vsrw_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsrw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+
+test_vsrw_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [0000001F, 0000001F, 0000001F, 0000001F]
+  vsrw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v4 [0000001F, 0000001F, 0000001F, 0000001F]
+
+test_vsrw_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000020, 00000020, 00000020, 00000020]
+  vsrw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000020, 00000020, 00000020, 00000020]
+
+test_vsrw_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000009, 00000009, 00000009, 00000009]
+  vsrw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [007FFFFF, 007FFFFF, 007FFFFF, 007FFFFF]
+  #_ REGISTER_OUT v4 [00000009, 00000009, 00000009, 00000009]
+
+test_vsrw_6:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000021, 00000021, 00000021, 00000021]
+  vsrw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_OUT v4 [00000021, 00000021, 00000021, 00000021]
+
+test_vsrw_7:
+  #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsrw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]