[Testing] Add a lot more missing instruction tests

src/xenia/cpu/ppc/testing/instr_addx.s

@@ -0,0 +1,90 @@
+test_addx_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000002000
+  add. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000003000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_addx_1_constant:
+  li r4, 0x1000
+  li r5, 0x2000
+  add. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000003000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_addx_overflow:
+  #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000001
+  add. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+  #_ REGISTER_OUT r12 0x0000000020000000
+
+test_addx_negative:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000001
+  add. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r12 0x0000000020000000
+
+test_addcx_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000002000
+  addc. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000003000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_addcx_overflow:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000001
+  addc. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r12 0x0000000020000000
+
+test_addex_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000002000
+  #_ REGISTER_IN r0 0x0000000020000000
+  mtxer r0
+  adde. r3, r4, r5
+  mfcr r12
+  mfxer r6
+  blr
+  #_ REGISTER_OUT r3 0x0000000000003001
+  #_ REGISTER_OUT r6 0x0000000000000000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_addmex_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r0 0x0000000000000000
+  mtxer r0
+  addme. r3, r4
+  mfcr r12
+  mfxer r6
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000FFF
+  #_ REGISTER_OUT r6 0x0000000020000000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_addzex_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r0 0x0000000000000000
+  mtxer r0
+  addze. r3, r4
+  mfcr r12
+  mfxer r6
+  blr
+  #_ REGISTER_OUT r3 0x0000000000001000
+  #_ REGISTER_OUT r6 0x0000000000000000
+  #_ REGISTER_OUT r12 0x0000000040000000

src/xenia/cpu/ppc/testing/instr_cntlzdx.s

@@ -0,0 +1,27 @@
+test_cntlzdx_1:
+  #_ REGISTER_IN r4 0x0000000000000001
+  cntlzd. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x000000000000003F
+  #_ REGISTER_OUT r4 0x0000000000000001
+
+test_cntlzdx_2:
+  #_ REGISTER_IN r4 0x8000000000000000
+  cntlzd. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x8000000000000000
+
+test_cntlzdx_3:
+  #_ REGISTER_IN r4 0x0000000000000000
+  cntlzd. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000040
+  #_ REGISTER_OUT r4 0x0000000000000000
+
+test_cntlzdx_4:
+  #_ REGISTER_IN r4 0x0000000100000000
+  cntlzd. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x000000000000001F
+  #_ REGISTER_OUT r4 0x0000000100000000

src/xenia/cpu/ppc/testing/instr_cntlzwx.s

@@ -0,0 +1,27 @@
+test_cntlzwx_1:
+  #_ REGISTER_IN r4 0x0000000000000001
+  cntlzw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x000000000000001F
+  #_ REGISTER_OUT r4 0x0000000000000001
+
+test_cntlzwx_2:
+  #_ REGISTER_IN r4 0x0000000080000000
+  cntlzw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000080000000
+
+test_cntlzwx_3:
+  #_ REGISTER_IN r4 0x0000000000000000
+  cntlzw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000020
+  #_ REGISTER_OUT r4 0x0000000000000000
+
+test_cntlzwx_4:
+  #_ REGISTER_IN r4 0x0000000000010000
+  cntlzw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x000000000000000F
+  #_ REGISTER_OUT r4 0x0000000000010000

src/xenia/cpu/ppc/testing/instr_dcbf.s

@@ -0,0 +1,31 @@
+test_dcbf_1:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 0
+  dcbf r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 0
+
+test_dcbf_2:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 64
+  dcbf r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 64
+
+test_dcbf_3:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x00001000
+  dcbf r4, r5
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x00001000
+
+test_dcbf_4:
+  #_ REGISTER_IN r4 0x00002000
+  #_ REGISTER_IN r5 128
+  dcbf r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00002000
+  #_ REGISTER_OUT r5 128

src/xenia/cpu/ppc/testing/instr_dcbst.s

@@ -0,0 +1,31 @@
+test_dcbst_1:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 0
+  dcbst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 0
+
+test_dcbst_2:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 64
+  dcbst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 64
+
+test_dcbst_3:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x00001000
+  dcbst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x00001000
+
+test_dcbst_4:
+  #_ REGISTER_IN r4 0x00002000
+  #_ REGISTER_IN r5 128
+  dcbst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00002000
+  #_ REGISTER_OUT r5 128

src/xenia/cpu/ppc/testing/instr_dcbt.s

@@ -0,0 +1,31 @@
+test_dcbt_1:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 0
+  dcbt r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 0
+
+test_dcbt_2:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 64
+  dcbt r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 64
+
+test_dcbt_3:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x00001000
+  dcbt r4, r5
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x00001000
+
+test_dcbt_4:
+  #_ REGISTER_IN r4 0x00002000
+  #_ REGISTER_IN r5 128
+  dcbt r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00002000
+  #_ REGISTER_OUT r5 128

src/xenia/cpu/ppc/testing/instr_dcbtst.s

@@ -0,0 +1,31 @@
+test_dcbtst_1:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 0
+  dcbtst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 0
+
+test_dcbtst_2:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 64
+  dcbtst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 64
+
+test_dcbtst_3:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x00001000
+  dcbtst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x00001000
+
+test_dcbtst_4:
+  #_ REGISTER_IN r4 0x00002000
+  #_ REGISTER_IN r5 128
+  dcbtst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00002000
+  #_ REGISTER_OUT r5 128

src/xenia/cpu/ppc/testing/instr_dcbz.s

@@ -0,0 +1,39 @@
+test_dcbz_1:
+  #_ MEMORY_IN 0x0000000010001000 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0
+  dcbz r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0
+  #_ MEMORY_OUT 10001000 00000000000000000000000000000000000000000000000000000000000000
+
+test_dcbz_2:
+  #_ MEMORY_IN 0x0000000010001040 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 64
+  dcbz r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 64
+  #_ MEMORY_OUT 10001040 00000000000000000000000000000000000000000000000000000000000000
+
+test_dcbz_3:
+  #_ MEMORY_IN 0x0000000010001000 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF]
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x0000000010001000
+  dcbz r4, r5
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x0000000010001000
+  #_ MEMORY_OUT 10001000 00000000000000000000000000000000000000000000000000000000000000
+
+test_dcbz_4:
+  #_ MEMORY_IN 0x0000000010001080 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 128
+  dcbz r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 128
+  #_ MEMORY_OUT 10001080 00000000000000000000000000000000000000000000000000000000000000

src/xenia/cpu/ppc/testing/instr_dcbz128.s

@@ -0,0 +1,28 @@
+test_dcbz128_1:
+  # Clear 128 bytes starting at aligned address
+  #_ MEMORY_IN 10001000 0102030405060708090A0B0C0D0E0F10111213141516171819191A1B1C1D1E1F202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F404142434445464748494A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F707172737475767778797A7B7C7D7E7F80
+  li r4, 0x1000
+  oris r4, r4, 0x1000
+  dcbz128 r0, r4
+  blr
+  #_ MEMORY_OUT 10001000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+
+test_dcbz128_2:
+  # Clear 128 bytes with non-zero base register
+  #_ MEMORY_IN 10002000 0102030405060708090A0B0C0D0E0F10111213141516171819191A1B1C1D1E1F202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F404142434445464748494A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F707172737475767778797A7B7C7D7E7F80
+  li r3, 0x1000
+  oris r3, r3, 0x1000
+  li r4, 0x1000
+  dcbz128 r3, r4
+  blr
+  #_ MEMORY_OUT 10002000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+
+test_dcbz128_3:
+  # Verify unaligned address is rounded down to 128-byte boundary
+  # Address 10003040 should clear block starting at 10003000
+  #_ MEMORY_IN 10003000 0102030405060708090A0B0C0D0E0F10111213141516171819191A1B1C1D1E1F202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F404142434445464748494A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F707172737475767778797A7B7C7D7E7F80
+  li r4, 0x3040
+  oris r4, r4, 0x1000
+  dcbz128 r0, r4
+  blr
+  #_ MEMORY_OUT 10003000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

src/xenia/cpu/ppc/testing/instr_divdx.s

@@ -0,0 +1,89 @@
+test_divdx_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000000010
+  divd. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000100
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_divdx_1_constant:
+  li r4, 0x1000
+  li r5, 0x10
+  divd. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000100
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_divdx_negative:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFF000
+  #_ REGISTER_IN r5 0x0000000000000010
+  divd. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF00
+  #_ REGISTER_OUT r12 0x0000000080000000
+
+test_divdx_by_zero:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  divd. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r12 0x0000000020000000
+
+test_divdux_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000000010
+  divdu. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000100
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_divdux_large:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000002
+  divdu. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r12 0x0000000080000000
+
+test_divwx_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000000010
+  divw. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000100
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_divwx_negative:
+  #_ REGISTER_IN r4 0x00000000FFFFF000
+  #_ REGISTER_IN r5 0x0000000000000010
+  divw. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFF00
+  #_ REGISTER_OUT r12 0x0000000080000000
+
+test_divwux_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000000010
+  divwu. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000100
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_divwux_large:
+  #_ REGISTER_IN r4 0x00000000FFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000002
+  divwu. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r12 0x0000000040000000

src/xenia/cpu/ppc/testing/instr_eieio.s

@@ -0,0 +1,13 @@
+test_eieio_1:
+  #_ REGISTER_IN r3 0x0000000000000001
+  eieio
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+
+test_eieio_2:
+  #_ REGISTER_IN r4 0x0000000012345678
+  #_ REGISTER_IN r5 0xABCDEF0123456789
+  eieio
+  blr
+  #_ REGISTER_OUT r4 0x0000000012345678
+  #_ REGISTER_OUT r5 0xABCDEF0123456789

src/xenia/cpu/ppc/testing/instr_eqvx.s

@@ -0,0 +1,35 @@
+test_eqvx_1:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  eqv. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_eqvx_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xAAAAAAAAAAAAAAAA
+  eqv. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xAAAAAAAAAAAAAAAA
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xAAAAAAAAAAAAAAAA
+
+test_eqvx_3:
+  #_ REGISTER_IN r4 0xAAAAAAAAAAAAAAAA
+  #_ REGISTER_IN r5 0x5555555555555555
+  eqv. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0xAAAAAAAAAAAAAAAA
+  #_ REGISTER_OUT r5 0x5555555555555555
+
+test_eqvx_4:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  #_ REGISTER_IN r5 0x123456789ABCDEF0
+  eqv. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x123456789ABCDEF0

src/xenia/cpu/ppc/testing/instr_extsbx.s

@@ -0,0 +1,27 @@
+test_extsbx_1:
+  #_ REGISTER_IN r4 0x000000000000007F
+  extsb. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007F
+  #_ REGISTER_OUT r4 0x000000000000007F
+
+test_extsbx_2:
+  #_ REGISTER_IN r4 0x0000000000000080
+  extsb. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
+  #_ REGISTER_OUT r4 0x0000000000000080
+
+test_extsbx_3:
+  #_ REGISTER_IN r4 0x00000000000000FF
+  extsb. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x00000000000000FF
+
+test_extsbx_4:
+  #_ REGISTER_IN r4 0x0000000000000001
+  extsb. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000000001

src/xenia/cpu/ppc/testing/instr_extshx.s

@@ -0,0 +1,27 @@
+test_extshx_1:
+  #_ REGISTER_IN r4 0x0000000000007FFF
+  extsh. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000007FFF
+  #_ REGISTER_OUT r4 0x0000000000007FFF
+
+test_extshx_2:
+  #_ REGISTER_IN r4 0x0000000000008000
+  extsh. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
+  #_ REGISTER_OUT r4 0x0000000000008000
+
+test_extshx_3:
+  #_ REGISTER_IN r4 0x000000000000FFFF
+  extsh. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x000000000000FFFF
+
+test_extshx_4:
+  #_ REGISTER_IN r4 0x0000000000000001
+  extsh. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000000001

src/xenia/cpu/ppc/testing/instr_extswx.s

@@ -0,0 +1,27 @@
+test_extswx_1:
+  #_ REGISTER_IN r4 0x000000007FFFFFFF
+  extsw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+
+test_extswx_2:
+  #_ REGISTER_IN r4 0x0000000080000000
+  extsw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+  #_ REGISTER_OUT r4 0x0000000080000000
+
+test_extswx_3:
+  #_ REGISTER_IN r4 0x00000000FFFFFFFF
+  extsw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x00000000FFFFFFFF
+
+test_extswx_4:
+  #_ REGISTER_IN r4 0x0000000000000001
+  extsw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000000001

src/xenia/cpu/ppc/testing/instr_fabsx.s

@@ -0,0 +1,27 @@
+test_fabsx_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  fabs. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [3FF0000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+
+test_fabsx_2:
+  #_ REGISTER_IN f4 [BFF0000000000000]
+  fabs. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [3FF0000000000000]
+  #_ REGISTER_OUT f4 [BFF0000000000000]
+
+test_fabsx_3:
+  #_ REGISTER_IN f4 [8000000000000000]
+  fabs. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [8000000000000000]
+
+test_fabsx_4:
+  #_ REGISTER_IN f4 [C005000000000000]
+  fabs. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [4005000000000000]
+  #_ REGISTER_OUT f4 [C005000000000000]

src/xenia/cpu/ppc/testing/instr_faddsx.s

@@ -0,0 +1,35 @@
+test_faddsx_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fadds. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4008000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]
+
+test_faddsx_2:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [BFF0000000000000]
+  fadds. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [BFF0000000000000]
+
+test_faddsx_3:
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4008000000000000]
+  fadds. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4010000000000000]
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4008000000000000]
+
+test_faddsx_4:
+  #_ REGISTER_IN f4 [0000000000000000]
+  #_ REGISTER_IN f5 [0000000000000000]
+  fadds. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [0000000000000000]
+  #_ REGISTER_OUT f5 [0000000000000000]

src/xenia/cpu/ppc/testing/instr_faddx.s

@@ -0,0 +1,35 @@
+test_faddx_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fadd. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4008000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]
+
+test_faddx_2:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [BFF0000000000000]
+  fadd. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [BFF0000000000000]
+
+test_faddx_3:
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4008000000000000]
+  fadd. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4010000000000000]
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4008000000000000]
+
+test_faddx_4:
+  #_ REGISTER_IN f4 [0000000000000000]
+  #_ REGISTER_IN f5 [0000000000000000]
+  fadd. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [0000000000000000]
+  #_ REGISTER_OUT f5 [0000000000000000]

src/xenia/cpu/ppc/testing/instr_fcfidx.s

@@ -0,0 +1,27 @@
+test_fcfidx_1:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fcfid. f3, f1
+  blr
+  #_ REGISTER_OUT f3 1.0
+  #_ REGISTER_OUT f1 0x0000000000000001
+
+test_fcfidx_2:
+  #_ REGISTER_IN f1 0xFFFFFFFFFFFFFFFF
+  fcfid. f3, f1
+  blr
+  #_ REGISTER_OUT f3 -1.0
+  #_ REGISTER_OUT f1 0xFFFFFFFFFFFFFFFF
+
+test_fcfidx_3:
+  #_ REGISTER_IN f1 0x0000000000000064
+  fcfid. f3, f1
+  blr
+  #_ REGISTER_OUT f3 100.0
+  #_ REGISTER_OUT f1 0x0000000000000064
+
+test_fcfidx_4:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fcfid. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0.0
+  #_ REGISTER_OUT f1 0x0000000000000000

src/xenia/cpu/ppc/testing/instr_fcmpo.s

@@ -0,0 +1,39 @@
+test_fcmpo_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fcmpo cr0, f4, f5
+  mfcr r3
+  blr
+  #_ REGISTER_OUT r3 0x20000000
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]
+
+test_fcmpo_2:
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fcmpo cr0, f4, f5
+  mfcr r3
+  blr
+  #_ REGISTER_OUT r3 0x20000000
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]
+
+test_fcmpo_3:
+  #_ REGISTER_IN f4 [4008000000000000]
+  #_ REGISTER_IN f5 [3FF0000000000000]
+  fcmpo cr0, f4, f5
+  mfcr r3
+  blr
+  #_ REGISTER_OUT r3 0x20000000
+  #_ REGISTER_OUT f4 [4008000000000000]
+  #_ REGISTER_OUT f5 [3FF0000000000000]
+
+test_fcmpo_4:
+  #_ REGISTER_IN f4 [0000000000000000]
+  #_ REGISTER_IN f5 [0000000000000000]
+  fcmpo cr0, f4, f5
+  mfcr r3
+  blr
+  #_ REGISTER_OUT r3 0x20000000
+  #_ REGISTER_OUT f4 [0000000000000000]
+  #_ REGISTER_OUT f5 [0000000000000000]

src/xenia/cpu/ppc/testing/instr_fcmpu.s

@@ -0,0 +1,39 @@
+test_fcmpu_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fcmpu cr0, f4, f5
+  mfcr r3
+  blr
+  #_ REGISTER_OUT r3 0x20000000
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]
+
+test_fcmpu_2:
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fcmpu cr0, f4, f5
+  mfcr r3
+  blr
+  #_ REGISTER_OUT r3 0x20000000
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]
+
+test_fcmpu_3:
+  #_ REGISTER_IN f4 [4008000000000000]
+  #_ REGISTER_IN f5 [3FF0000000000000]
+  fcmpu cr0, f4, f5
+  mfcr r3
+  blr
+  #_ REGISTER_OUT r3 0x20000000
+  #_ REGISTER_OUT f4 [4008000000000000]
+  #_ REGISTER_OUT f5 [3FF0000000000000]
+
+test_fcmpu_4:
+  #_ REGISTER_IN f4 [0000000000000000]
+  #_ REGISTER_IN f5 [0000000000000000]
+  fcmpu cr0, f4, f5
+  mfcr r3
+  blr
+  #_ REGISTER_OUT r3 0x20000000
+  #_ REGISTER_OUT f4 [0000000000000000]
+  #_ REGISTER_OUT f5 [0000000000000000]

src/xenia/cpu/ppc/testing/instr_fctidx.s

@@ -0,0 +1,27 @@
+test_fctidx_1:
+  #_ REGISTER_IN f1 3.7
+  fctid. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0x0000000000000004
+  #_ REGISTER_OUT f1 3.7
+
+test_fctidx_2:
+  #_ REGISTER_IN f1 -2.3
+  fctid. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT f1 -2.3
+
+test_fctidx_3:
+  #_ REGISTER_IN f1 100.9
+  fctid. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0x0000000000000065
+  #_ REGISTER_OUT f1 100.9
+
+test_fctidx_4:
+  #_ REGISTER_IN f1 0.0
+  fctid. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0x0000000000000000
+  #_ REGISTER_OUT f1 0.0

src/xenia/cpu/ppc/testing/instr_fctidzx.s

@@ -0,0 +1,27 @@
+test_fctidzx_1:
+  #_ REGISTER_IN f1 3.7
+  fctidz. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0x0000000000000003
+  #_ REGISTER_OUT f1 3.7
+
+test_fctidzx_2:
+  #_ REGISTER_IN f1 -2.9
+  fctidz. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT f1 -2.9
+
+test_fctidzx_3:
+  #_ REGISTER_IN f1 100.1
+  fctidz. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0x0000000000000064
+  #_ REGISTER_OUT f1 100.1
+
+test_fctidzx_4:
+  #_ REGISTER_IN f1 -0.5
+  fctidz. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0x0000000000000000
+  #_ REGISTER_OUT f1 -0.5

src/xenia/cpu/ppc/testing/instr_fctiwx.s

@@ -0,0 +1,27 @@
+test_fctiwx_1:
+  #_ REGISTER_IN f1 3.7
+  fctiw. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0x0000000000000004
+  #_ REGISTER_OUT f1 3.7
+
+test_fctiwx_2:
+  #_ REGISTER_IN f1 -2.3
+  fctiw. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT f1 -2.3
+
+test_fctiwx_3:
+  #_ REGISTER_IN f1 100.9
+  fctiw. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0x0000000000000065
+  #_ REGISTER_OUT f1 100.9
+
+test_fctiwx_4:
+  #_ REGISTER_IN f1 0.0
+  fctiw. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0x0000000000000000
+  #_ REGISTER_OUT f1 0.0

src/xenia/cpu/ppc/testing/instr_fctiwzx.s

@@ -0,0 +1,27 @@
+test_fctiwzx_1:
+  #_ REGISTER_IN f1 3.7
+  fctiwz. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0x0000000000000003
+  #_ REGISTER_OUT f1 3.7
+
+test_fctiwzx_2:
+  #_ REGISTER_IN f1 -2.9
+  fctiwz. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT f1 -2.9
+
+test_fctiwzx_3:
+  #_ REGISTER_IN f1 100.1
+  fctiwz. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0x0000000000000064
+  #_ REGISTER_OUT f1 100.1
+
+test_fctiwzx_4:
+  #_ REGISTER_IN f1 -0.5
+  fctiwz. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0x0000000000000000
+  #_ REGISTER_OUT f1 -0.5

src/xenia/cpu/ppc/testing/instr_fdivsx.s

@@ -0,0 +1,35 @@
+test_fdivsx_1:
+  #_ REGISTER_IN f1 6.0
+  #_ REGISTER_IN f2 2.0
+  fdivs. f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 3.0
+  #_ REGISTER_OUT f1 6.0
+  #_ REGISTER_OUT f2 2.0
+
+test_fdivsx_2:
+  #_ REGISTER_IN f1 1.0
+  #_ REGISTER_IN f2 -1.0
+  fdivs. f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 -1.0
+  #_ REGISTER_OUT f1 1.0
+  #_ REGISTER_OUT f2 -1.0
+
+test_fdivsx_3:
+  #_ REGISTER_IN f1 2.0
+  #_ REGISTER_IN f2 2.0
+  fdivs. f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 1.0
+  #_ REGISTER_OUT f1 2.0
+  #_ REGISTER_OUT f2 2.0
+
+test_fdivsx_4:
+  #_ REGISTER_IN f1 4.0
+  #_ REGISTER_IN f2 2.0
+  fdivs. f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 2.0
+  #_ REGISTER_OUT f1 4.0
+  #_ REGISTER_OUT f2 2.0

src/xenia/cpu/ppc/testing/instr_fdivx.s

@@ -0,0 +1,35 @@
+test_fdivx_1:
+  #_ REGISTER_IN f1 6.0
+  #_ REGISTER_IN f2 2.0
+  fdiv. f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 3.0
+  #_ REGISTER_OUT f1 6.0
+  #_ REGISTER_OUT f2 2.0
+
+test_fdivx_2:
+  #_ REGISTER_IN f1 1.0
+  #_ REGISTER_IN f2 -1.0
+  fdiv. f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 -1.0
+  #_ REGISTER_OUT f1 1.0
+  #_ REGISTER_OUT f2 -1.0
+
+test_fdivx_3:
+  #_ REGISTER_IN f1 2.0
+  #_ REGISTER_IN f2 2.0
+  fdiv. f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 1.0
+  #_ REGISTER_OUT f1 2.0
+  #_ REGISTER_OUT f2 2.0
+
+test_fdivx_4:
+  #_ REGISTER_IN f1 4.0
+  #_ REGISTER_IN f2 2.0
+  fdiv. f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 2.0
+  #_ REGISTER_OUT f1 4.0
+  #_ REGISTER_OUT f2 2.0

src/xenia/cpu/ppc/testing/instr_fmaddsx.s

@@ -0,0 +1,43 @@
+test_fmaddsx_1:
+  #_ REGISTER_IN f1 2.0
+  #_ REGISTER_IN f2 3.0
+  #_ REGISTER_IN f3 4.0
+  fmadds. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 10.0
+  #_ REGISTER_OUT f1 2.0
+  #_ REGISTER_OUT f2 3.0
+  #_ REGISTER_OUT f3 4.0
+
+test_fmaddsx_2:
+  #_ REGISTER_IN f1 -1.5
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 1.0
+  fmadds. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -2.0
+  #_ REGISTER_OUT f1 -1.5
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 1.0
+
+test_fmaddsx_3:
+  #_ REGISTER_IN f1 0.5
+  #_ REGISTER_IN f2 0.5
+  #_ REGISTER_IN f3 0.25
+  fmadds. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 0.5
+  #_ REGISTER_OUT f1 0.5
+  #_ REGISTER_OUT f2 0.5
+  #_ REGISTER_OUT f3 0.25
+
+test_fmaddsx_4:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 100.0
+  #_ REGISTER_IN f3 5.0
+  fmadds. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 5.0
+  #_ REGISTER_OUT f1 0.0
+  #_ REGISTER_OUT f2 100.0
+  #_ REGISTER_OUT f3 5.0

src/xenia/cpu/ppc/testing/instr_fmaddx.s

@@ -0,0 +1,43 @@
+test_fmaddx_1:
+  #_ REGISTER_IN f1 2.0
+  #_ REGISTER_IN f2 3.0
+  #_ REGISTER_IN f3 4.0
+  fmadd. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 10.0
+  #_ REGISTER_OUT f1 2.0
+  #_ REGISTER_OUT f2 3.0
+  #_ REGISTER_OUT f3 4.0
+
+test_fmaddx_2:
+  #_ REGISTER_IN f1 -1.5
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 1.0
+  fmadd. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -2.0
+  #_ REGISTER_OUT f1 -1.5
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 1.0
+
+test_fmaddx_3:
+  #_ REGISTER_IN f1 0.5
+  #_ REGISTER_IN f2 0.5
+  #_ REGISTER_IN f3 0.25
+  fmadd. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 0.5
+  #_ REGISTER_OUT f1 0.5
+  #_ REGISTER_OUT f2 0.5
+  #_ REGISTER_OUT f3 0.25
+
+test_fmaddx_4:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 100.0
+  #_ REGISTER_IN f3 5.0
+  fmadd. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 5.0
+  #_ REGISTER_OUT f1 0.0
+  #_ REGISTER_OUT f2 100.0
+  #_ REGISTER_OUT f3 5.0

src/xenia/cpu/ppc/testing/instr_fmrx.s

@@ -0,0 +1,27 @@
+test_fmrx_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  fmr. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [3FF0000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+
+test_fmrx_2:
+  #_ REGISTER_IN f4 [BFF0000000000000]
+  fmr. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [BFF0000000000000]
+  #_ REGISTER_OUT f4 [BFF0000000000000]
+
+test_fmrx_3:
+  #_ REGISTER_IN f4 [0000000000000000]
+  fmr. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [0000000000000000]
+
+test_fmrx_4:
+  #_ REGISTER_IN f4 [4005000000000000]
+  fmr. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [4005000000000000]
+  #_ REGISTER_OUT f4 [4005000000000000]

src/xenia/cpu/ppc/testing/instr_fmsubsx.s

@@ -0,0 +1,43 @@
+test_fmsubsx_1:
+  #_ REGISTER_IN f1 2.0
+  #_ REGISTER_IN f2 3.0
+  #_ REGISTER_IN f3 4.0
+  fmsubs. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 2.0
+  #_ REGISTER_OUT f1 2.0
+  #_ REGISTER_OUT f2 3.0
+  #_ REGISTER_OUT f3 4.0
+
+test_fmsubsx_2:
+  #_ REGISTER_IN f1 -1.5
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 1.0
+  fmsubs. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -4.0
+  #_ REGISTER_OUT f1 -1.5
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 1.0
+
+test_fmsubsx_3:
+  #_ REGISTER_IN f1 0.5
+  #_ REGISTER_IN f2 0.5
+  #_ REGISTER_IN f3 0.25
+  fmsubs. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 0.0
+  #_ REGISTER_OUT f1 0.5
+  #_ REGISTER_OUT f2 0.5
+  #_ REGISTER_OUT f3 0.25
+
+test_fmsubsx_4:
+  #_ REGISTER_IN f1 10.0
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 5.0
+  fmsubs. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 15.0
+  #_ REGISTER_OUT f1 10.0
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 5.0

src/xenia/cpu/ppc/testing/instr_fmsubx.s

@@ -0,0 +1,43 @@
+test_fmsubx_1:
+  #_ REGISTER_IN f1 2.0
+  #_ REGISTER_IN f2 3.0
+  #_ REGISTER_IN f3 4.0
+  fmsub. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 2.0
+  #_ REGISTER_OUT f1 2.0
+  #_ REGISTER_OUT f2 3.0
+  #_ REGISTER_OUT f3 4.0
+
+test_fmsubx_2:
+  #_ REGISTER_IN f1 -1.5
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 1.0
+  fmsub. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -4.0
+  #_ REGISTER_OUT f1 -1.5
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 1.0
+
+test_fmsubx_3:
+  #_ REGISTER_IN f1 0.5
+  #_ REGISTER_IN f2 0.5
+  #_ REGISTER_IN f3 0.25
+  fmsub. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 0.0
+  #_ REGISTER_OUT f1 0.5
+  #_ REGISTER_OUT f2 0.5
+  #_ REGISTER_OUT f3 0.25
+
+test_fmsubx_4:
+  #_ REGISTER_IN f1 10.0
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 5.0
+  fmsub. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 15.0
+  #_ REGISTER_OUT f1 10.0
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 5.0

src/xenia/cpu/ppc/testing/instr_fmulsx.s

@@ -0,0 +1,35 @@
+test_fmulsx_1:
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4008000000000000]
+  fmuls. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4018000000000000]
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4008000000000000]
+
+test_fmulsx_2:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [BFF0000000000000]
+  fmuls. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [BFF0000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [BFF0000000000000]
+
+test_fmulsx_3:
+  #_ REGISTER_IN f4 [0000000000000000]
+  #_ REGISTER_IN f5 [4008000000000000]
+  fmuls. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [0000000000000000]
+  #_ REGISTER_OUT f5 [4008000000000000]
+
+test_fmulsx_4:
+  #_ REGISTER_IN f4 [3FE0000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fmuls. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [3FF0000000000000]
+  #_ REGISTER_OUT f4 [3FE0000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]

src/xenia/cpu/ppc/testing/instr_fmulx.s

@@ -0,0 +1,35 @@
+test_fmulx_1:
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4008000000000000]
+  fmul. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4018000000000000]
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4008000000000000]
+
+test_fmulx_2:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [BFF0000000000000]
+  fmul. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [BFF0000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [BFF0000000000000]
+
+test_fmulx_3:
+  #_ REGISTER_IN f4 [0000000000000000]
+  #_ REGISTER_IN f5 [4008000000000000]
+  fmul. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [0000000000000000]
+  #_ REGISTER_OUT f5 [4008000000000000]
+
+test_fmulx_4:
+  #_ REGISTER_IN f4 [3FE0000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fmul. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [3FF0000000000000]
+  #_ REGISTER_OUT f4 [3FE0000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]

src/xenia/cpu/ppc/testing/instr_fnabsx.s

@@ -0,0 +1,27 @@
+test_fnabsx_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  fnabs. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [BFF0000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+
+test_fnabsx_2:
+  #_ REGISTER_IN f4 [BFF0000000000000]
+  fnabs. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [BFF0000000000000]
+  #_ REGISTER_OUT f4 [BFF0000000000000]
+
+test_fnabsx_3:
+  #_ REGISTER_IN f4 [0000000000000000]
+  fnabs. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [8000000000000000]
+  #_ REGISTER_OUT f4 [0000000000000000]
+
+test_fnabsx_4:
+  #_ REGISTER_IN f4 [4005000000000000]
+  fnabs. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [C005000000000000]
+  #_ REGISTER_OUT f4 [4005000000000000]

src/xenia/cpu/ppc/testing/instr_fnegx.s

@@ -0,0 +1,27 @@
+test_fnegx_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  fneg. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [BFF0000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+
+test_fnegx_2:
+  #_ REGISTER_IN f4 [BFF0000000000000]
+  fneg. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [3FF0000000000000]
+  #_ REGISTER_OUT f4 [BFF0000000000000]
+
+test_fnegx_3:
+  #_ REGISTER_IN f4 [0000000000000000]
+  fneg. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [8000000000000000]
+  #_ REGISTER_OUT f4 [0000000000000000]
+
+test_fnegx_4:
+  #_ REGISTER_IN f4 [4005000000000000]
+  fneg. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [C005000000000000]
+  #_ REGISTER_OUT f4 [4005000000000000]

src/xenia/cpu/ppc/testing/instr_fnmaddsx.s

@@ -0,0 +1,43 @@
+test_fnmaddsx_1:
+  #_ REGISTER_IN f1 2.0
+  #_ REGISTER_IN f2 3.0
+  #_ REGISTER_IN f3 4.0
+  fnmadds. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -10.0
+  #_ REGISTER_OUT f1 2.0
+  #_ REGISTER_OUT f2 3.0
+  #_ REGISTER_OUT f3 4.0
+
+test_fnmaddsx_2:
+  #_ REGISTER_IN f1 -1.5
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 1.0
+  fnmadds. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 2.0
+  #_ REGISTER_OUT f1 -1.5
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 1.0
+
+test_fnmaddsx_3:
+  #_ REGISTER_IN f1 0.5
+  #_ REGISTER_IN f2 0.5
+  #_ REGISTER_IN f3 0.25
+  fnmadds. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -0.5
+  #_ REGISTER_OUT f1 0.5
+  #_ REGISTER_OUT f2 0.5
+  #_ REGISTER_OUT f3 0.25
+
+test_fnmaddsx_4:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 100.0
+  #_ REGISTER_IN f3 5.0
+  fnmadds. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -5.0
+  #_ REGISTER_OUT f1 0.0
+  #_ REGISTER_OUT f2 100.0
+  #_ REGISTER_OUT f3 5.0

src/xenia/cpu/ppc/testing/instr_fnmaddx.s

@@ -0,0 +1,43 @@
+test_fnmaddx_1:
+  #_ REGISTER_IN f1 2.0
+  #_ REGISTER_IN f2 3.0
+  #_ REGISTER_IN f3 4.0
+  fnmadd. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -10.0
+  #_ REGISTER_OUT f1 2.0
+  #_ REGISTER_OUT f2 3.0
+  #_ REGISTER_OUT f3 4.0
+
+test_fnmaddx_2:
+  #_ REGISTER_IN f1 -1.5
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 1.0
+  fnmadd. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 2.0
+  #_ REGISTER_OUT f1 -1.5
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 1.0
+
+test_fnmaddx_3:
+  #_ REGISTER_IN f1 0.5
+  #_ REGISTER_IN f2 0.5
+  #_ REGISTER_IN f3 0.25
+  fnmadd. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -0.5
+  #_ REGISTER_OUT f1 0.5
+  #_ REGISTER_OUT f2 0.5
+  #_ REGISTER_OUT f3 0.25
+
+test_fnmaddx_4:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 100.0
+  #_ REGISTER_IN f3 5.0
+  fnmadd. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -5.0
+  #_ REGISTER_OUT f1 0.0
+  #_ REGISTER_OUT f2 100.0
+  #_ REGISTER_OUT f3 5.0

src/xenia/cpu/ppc/testing/instr_fnmsubsx.s

@@ -0,0 +1,43 @@
+test_fnmsubsx_1:
+  #_ REGISTER_IN f1 2.0
+  #_ REGISTER_IN f2 3.0
+  #_ REGISTER_IN f3 4.0
+  fnmsubs. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -2.0
+  #_ REGISTER_OUT f1 2.0
+  #_ REGISTER_OUT f2 3.0
+  #_ REGISTER_OUT f3 4.0
+
+test_fnmsubsx_2:
+  #_ REGISTER_IN f1 -1.5
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 1.0
+  fnmsubs. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 4.0
+  #_ REGISTER_OUT f1 -1.5
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 1.0
+
+test_fnmsubsx_3:
+  #_ REGISTER_IN f1 0.5
+  #_ REGISTER_IN f2 0.5
+  #_ REGISTER_IN f3 0.25
+  fnmsubs. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 0.0
+  #_ REGISTER_OUT f1 0.5
+  #_ REGISTER_OUT f2 0.5
+  #_ REGISTER_OUT f3 0.25
+
+test_fnmsubsx_4:
+  #_ REGISTER_IN f1 10.0
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 5.0
+  fnmsubs. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -15.0
+  #_ REGISTER_OUT f1 10.0
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 5.0

src/xenia/cpu/ppc/testing/instr_fnmsubx.s

@@ -0,0 +1,43 @@
+test_fnmsubx_1:
+  #_ REGISTER_IN f1 2.0
+  #_ REGISTER_IN f2 3.0
+  #_ REGISTER_IN f3 4.0
+  fnmsub. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -2.0
+  #_ REGISTER_OUT f1 2.0
+  #_ REGISTER_OUT f2 3.0
+  #_ REGISTER_OUT f3 4.0
+
+test_fnmsubx_2:
+  #_ REGISTER_IN f1 -1.5
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 1.0
+  fnmsub. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 4.0
+  #_ REGISTER_OUT f1 -1.5
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 1.0
+
+test_fnmsubx_3:
+  #_ REGISTER_IN f1 0.5
+  #_ REGISTER_IN f2 0.5
+  #_ REGISTER_IN f3 0.25
+  fnmsub. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 0.0
+  #_ REGISTER_OUT f1 0.5
+  #_ REGISTER_OUT f2 0.5
+  #_ REGISTER_OUT f3 0.25
+
+test_fnmsubx_4:
+  #_ REGISTER_IN f1 10.0
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 5.0
+  fnmsub. f5, f1, f2, f3
+  blr
+  #_ REGISTER_OUT f5 -15.0
+  #_ REGISTER_OUT f1 10.0
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 5.0

src/xenia/cpu/ppc/testing/instr_fresx.s

@@ -0,0 +1,27 @@
+test_fresx_1:
+  #_ REGISTER_IN f1 2.0
+  fres. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0.5
+  #_ REGISTER_OUT f1 2.0
+
+test_fresx_2:
+  #_ REGISTER_IN f1 4.0
+  fres. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0.25
+  #_ REGISTER_OUT f1 4.0
+
+test_fresx_3:
+  #_ REGISTER_IN f1 0.5
+  fres. f3, f1
+  blr
+  #_ REGISTER_OUT f3 2.0
+  #_ REGISTER_OUT f1 0.5
+
+test_fresx_4:
+  #_ REGISTER_IN f1 1.0
+  fres. f3, f1
+  blr
+  #_ REGISTER_OUT f3 1.0
+  #_ REGISTER_OUT f1 1.0

src/xenia/cpu/ppc/testing/instr_frspx.s

@@ -0,0 +1,27 @@
+test_frspx_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  frsp. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [3FF0000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+
+test_frspx_2:
+  #_ REGISTER_IN f4 [4000000000000000]
+  frsp. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [4000000000000000]
+  #_ REGISTER_OUT f4 [4000000000000000]
+
+test_frspx_3:
+  #_ REGISTER_IN f4 [0000000000000000]
+  frsp. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [0000000000000000]
+
+test_frspx_4:
+  #_ REGISTER_IN f4 [4008000000000000]
+  frsp. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [4008000000000000]
+  #_ REGISTER_OUT f4 [4008000000000000]

src/xenia/cpu/ppc/testing/instr_frsqrtex.s

@@ -0,0 +1,27 @@
+test_frsqrtex_1:
+  #_ REGISTER_IN f1 4.0
+  frsqrte. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0.48535156250000000
+  #_ REGISTER_OUT f1 4.0
+
+test_frsqrtex_2:
+  #_ REGISTER_IN f1 16.0
+  frsqrte. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0.24267578125000000
+  #_ REGISTER_OUT f1 16.0
+
+test_frsqrtex_3:
+  #_ REGISTER_IN f1 1.0
+  frsqrte. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0.97070312500000000
+  #_ REGISTER_OUT f1 1.0
+
+test_frsqrtex_4:
+  #_ REGISTER_IN f1 9.0
+  frsqrte. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0.32421875000000000
+  #_ REGISTER_OUT f1 9.0

src/xenia/cpu/ppc/testing/instr_fselx.s

@@ -0,0 +1,43 @@
+test_fselx_1:
+  #_ REGISTER_IN f3 [3FF0000000000000]
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4008000000000000]
+  fsel. f6, f3, f4, f5
+  blr
+  #_ REGISTER_OUT f6 [4000000000000000]
+  #_ REGISTER_OUT f3 [3FF0000000000000]
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4008000000000000]
+
+test_fselx_2:
+  #_ REGISTER_IN f3 [BFF0000000000000]
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4008000000000000]
+  fsel. f6, f3, f4, f5
+  blr
+  #_ REGISTER_OUT f6 [4008000000000000]
+  #_ REGISTER_OUT f3 [BFF0000000000000]
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4008000000000000]
+
+test_fselx_3:
+  #_ REGISTER_IN f3 [0000000000000000]
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4008000000000000]
+  fsel. f6, f3, f4, f5
+  blr
+  #_ REGISTER_OUT f6 [4000000000000000]
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4008000000000000]
+
+test_fselx_4:
+  #_ REGISTER_IN f3 [4010000000000000]
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4008000000000000]
+  fsel. f6, f3, f4, f5
+  blr
+  #_ REGISTER_OUT f6 [4000000000000000]
+  #_ REGISTER_OUT f3 [4010000000000000]
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4008000000000000]

src/xenia/cpu/ppc/testing/instr_fsqrtsx.s

@@ -0,0 +1,27 @@
+test_fsqrtsx_1:
+  #_ REGISTER_IN f1 4.0
+  fsqrts. f3, f1
+  blr
+  #_ REGISTER_OUT f3 2.0
+  #_ REGISTER_OUT f1 4.0
+
+test_fsqrtsx_2:
+  #_ REGISTER_IN f1 16.0
+  fsqrts. f3, f1
+  blr
+  #_ REGISTER_OUT f3 4.0
+  #_ REGISTER_OUT f1 16.0
+
+test_fsqrtsx_3:
+  #_ REGISTER_IN f1 1.0
+  fsqrts. f3, f1
+  blr
+  #_ REGISTER_OUT f3 1.0
+  #_ REGISTER_OUT f1 1.0
+
+test_fsqrtsx_4:
+  #_ REGISTER_IN f1 9.0
+  fsqrts. f3, f1
+  blr
+  #_ REGISTER_OUT f3 3.0
+  #_ REGISTER_OUT f1 9.0

src/xenia/cpu/ppc/testing/instr_fsqrtx.s

@@ -0,0 +1,27 @@
+test_fsqrtx_1:
+  #_ REGISTER_IN f1 4.0
+  fsqrt. f3, f1
+  blr
+  #_ REGISTER_OUT f3 2.0
+  #_ REGISTER_OUT f1 4.0
+
+test_fsqrtx_2:
+  #_ REGISTER_IN f1 16.0
+  fsqrt. f3, f1
+  blr
+  #_ REGISTER_OUT f3 4.0
+  #_ REGISTER_OUT f1 16.0
+
+test_fsqrtx_3:
+  #_ REGISTER_IN f1 1.0
+  fsqrt. f3, f1
+  blr
+  #_ REGISTER_OUT f3 1.0
+  #_ REGISTER_OUT f1 1.0
+
+test_fsqrtx_4:
+  #_ REGISTER_IN f1 9.0
+  fsqrt. f3, f1
+  blr
+  #_ REGISTER_OUT f3 3.0
+  #_ REGISTER_OUT f1 9.0

src/xenia/cpu/ppc/testing/instr_fsubsx.s

@@ -0,0 +1,35 @@
+test_fsubsx_1:
+  #_ REGISTER_IN f4 [4008000000000000]
+  #_ REGISTER_IN f5 [3FF0000000000000]
+  fsubs. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4000000000000000]
+  #_ REGISTER_OUT f4 [4008000000000000]
+  #_ REGISTER_OUT f5 [3FF0000000000000]
+
+test_fsubsx_2:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [3FF0000000000000]
+  fsubs. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [3FF0000000000000]
+
+test_fsubsx_3:
+  #_ REGISTER_IN f4 [4010000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fsubs. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4008000000000000]
+  #_ REGISTER_OUT f4 [4010000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]
+
+test_fsubsx_4:
+  #_ REGISTER_IN f4 [0000000000000000]
+  #_ REGISTER_IN f5 [0000000000000000]
+  fsubs. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [0000000000000000]
+  #_ REGISTER_OUT f5 [0000000000000000]

src/xenia/cpu/ppc/testing/instr_fsubx.s

@@ -0,0 +1,35 @@
+test_fsubx_1:
+  #_ REGISTER_IN f4 [4008000000000000]
+  #_ REGISTER_IN f5 [3FF0000000000000]
+  fsub. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4000000000000000]
+  #_ REGISTER_OUT f4 [4008000000000000]
+  #_ REGISTER_OUT f5 [3FF0000000000000]
+
+test_fsubx_2:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [3FF0000000000000]
+  fsub. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [3FF0000000000000]
+
+test_fsubx_3:
+  #_ REGISTER_IN f4 [4010000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fsub. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4008000000000000]
+  #_ REGISTER_OUT f4 [4010000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]
+
+test_fsubx_4:
+  #_ REGISTER_IN f4 [0000000000000000]
+  #_ REGISTER_IN f5 [0000000000000000]
+  fsub. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [0000000000000000]
+  #_ REGISTER_OUT f5 [0000000000000000]

src/xenia/cpu/ppc/testing/instr_icbi.s

@@ -0,0 +1,31 @@
+test_icbi_1:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 0
+  icbi r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 0
+
+test_icbi_2:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 64
+  icbi r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 64
+
+test_icbi_3:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x00001000
+  icbi r4, r5
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x00001000
+
+test_icbi_4:
+  #_ REGISTER_IN r4 0x00002000
+  #_ REGISTER_IN r5 128
+  icbi r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00002000
+  #_ REGISTER_OUT r5 128

src/xenia/cpu/ppc/testing/instr_isync.s

@@ -0,0 +1,13 @@
+test_isync_1:
+  #_ REGISTER_IN r3 0x0000000000000001
+  isync
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+
+test_isync_2:
+  #_ REGISTER_IN r4 0x0000000012345678
+  #_ REGISTER_IN r5 0xABCDEF0123456789
+  isync
+  blr
+  #_ REGISTER_OUT r4 0x0000000012345678
+  #_ REGISTER_OUT r5 0xABCDEF0123456789

src/xenia/cpu/ppc/testing/instr_lbz.s

@@ -0,0 +1,50 @@
+test_lbz_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lbz r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lbz_offset:
+  #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lbz r3, 4(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000033
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lbzu_1:
+  #_ MEMORY_IN 0x0000000010001000 [AA, BB, CC, DD, EE, FF, 00, 11]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lbzu r3, 4(r4)
+  blr
+  #_ REGISTER_OUT r3 0x00000000000000CC
+  #_ REGISTER_OUT r4 0x0000000010001004
+
+test_lbzx_1:
+  #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 9A, BC, DE, F0]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000003
+  lbzx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000003
+
+test_lbzux_1:
+  #_ MEMORY_IN 0x0000000010001000 [FF, EE, DD, CC, BB, AA, 99, 88]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000005
+  lbzux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001005
+
+test_lbz_max:
+  #_ MEMORY_IN 0x0000000010001000 [FF, 00, 7F, 80, 01, FE, 02, FD]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lbz r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001000

src/xenia/cpu/ppc/testing/instr_lbzu.s

@@ -0,0 +1,35 @@
+test_lbzu_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, 00, 00, 00, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lbzu r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lbzu_2:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, CD, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lbzu r3, 4(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001004
+
+test_lbzux_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, EF, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000006
+  lbzux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001006
+  #_ REGISTER_OUT r5 0x0000000000000006
+
+test_lbzux_2:
+  #_ MEMORY_IN 0x0000000010001000 [12, 00, 00, 00, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  lbzux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000000

src/xenia/cpu/ppc/testing/instr_ld.s

@@ -0,0 +1,43 @@
+test_ld_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A, BC, DE, F0, 11]
+  #_ REGISTER_IN r4 0x0000000010001000
+  ld r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x000BCD00EF001200
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_ld_offset:
+  #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88, 99, AA, BB, CC, DD, EE, FF, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  ld r3, 8(r4)
+  blr
+  #_ REGISTER_OUT r3 0x5500660077008800
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_ldu_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, AA, BB, CC, DD, EE, FF, 00, 11]
+  #_ REGISTER_IN r4 0x0000000010001000
+  ldu r3, 8(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001008
+
+test_ldx_1:
+  #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 9A, BC, DE, F0, FE, DC, BA, 98, 76, 54, 32, 10]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000008
+  ldx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x9A00BC00DE00F000
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000008
+
+test_ldux_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, FF, EE, DD, CC, BB, AA, 99, 88]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000010
+  ldux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001010
+  #_ REGISTER_OUT r5 0x0000000000000010

src/xenia/cpu/ppc/testing/instr_ldu.s

@@ -0,0 +1,35 @@
+test_ldu_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 90]
+  #_ REGISTER_IN r4 0x0000000010001000
+  ldu r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x000BCD00EF001200
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_ldu_2:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 12, 34, 56, 78, 9A, BC, DE, F0]
+  #_ REGISTER_IN r4 0x0000000010001000
+  ldu r3, 8(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001008
+
+test_ldux_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, FE, DC, BA, 98, 76, 54, 32, 10]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000008
+  ldux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001008
+  #_ REGISTER_OUT r5 0x0000000000000008
+
+test_ldux_2:
+  #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  ldux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0001220033004400
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000000

src/xenia/cpu/ppc/testing/instr_lfd.s

@@ -0,0 +1,43 @@
+test_lfd_1:
+  #_ MEMORY_IN 0x0000000010001000 [3F, F0, 00, 00, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lfd f3, 0(r4)
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT f3 0x000FF00000000000
+
+test_lfd_offset:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 40, 00, 00, 00, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lfd f3, 8(r4)
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT f3 0x0000000000000000
+
+test_lfdu_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 40, 08, 00, 00, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lfdu f3, 8(r4)
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001008
+  #_ REGISTER_OUT f3 0x0000000000000000
+
+test_lfdx_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 40, 10, 00, 00, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000008
+  lfdx f3, r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000008
+  #_ REGISTER_OUT f3 0x0000000000000000
+
+test_lfdux_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 40, 14, 00, 00, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000008
+  lfdux f3, r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001008
+  #_ REGISTER_OUT r5 0x0000000000000008
+  #_ REGISTER_OUT f3 0x0000000000000000

src/xenia/cpu/ppc/testing/instr_lfs.s

@@ -0,0 +1,43 @@
+test_lfs_1:
+  #_ MEMORY_IN 0x0000000010001000 [3F, 80, 00, 00, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lfs f3, 0(r4)
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT f3 0x37DF000000000000
+
+test_lfs_offset:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 40, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lfs f3, 4(r4)
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT f3 0x0000000000000000
+
+test_lfsu_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 40, 40, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lfsu f3, 4(r4)
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001004
+  #_ REGISTER_OUT f3 0x0000000000000000
+
+test_lfsx_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 40, 80, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000004
+  lfsx f3, r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000004
+  #_ REGISTER_OUT f3 0x0000000000000000
+
+test_lfsux_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 40, A0, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000004
+  lfsux f3, r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001004
+  #_ REGISTER_OUT r5 0x0000000000000004
+  #_ REGISTER_OUT f3 0x0000000000000000

src/xenia/cpu/ppc/testing/instr_lha.s

@@ -0,0 +1,43 @@
+test_lha_positive:
+  #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 7F, FF, 00, 01]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lha r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000002
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lha_negative:
+  #_ MEMORY_IN 0x0000000010001000 [FF, FF, 80, 00, 80, 01, AA, BB]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lha r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x000000000000000F
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lhau_positive:
+  #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lhau r3, 4(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000003300
+  #_ REGISTER_OUT r4 0x0000000010001004
+
+test_lhax_negative:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 80, 00, FF, FF]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000004
+  lhax r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000004
+
+test_lhaux_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, AA, BB]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000006
+  lhaux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001006
+  #_ REGISTER_OUT r5 0x0000000000000006

src/xenia/cpu/ppc/testing/instr_lhau.s

@@ -0,0 +1,35 @@
+test_lhau_1:
+  #_ MEMORY_IN 0x0000000010001000 [7F, FF, 00, 00, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lhau r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x000000000000000F
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lhau_2:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 80, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lhau r3, 4(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001004
+
+test_lhaux_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 12, 34]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000006
+  lhaux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001006
+  #_ REGISTER_OUT r5 0x0000000000000006
+
+test_lhaux_2:
+  #_ MEMORY_IN 0x0000000010001000 [FF, FF, 00, 00, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  lhaux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000000000000F
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000000

src/xenia/cpu/ppc/testing/instr_lhbrx.s

@@ -0,0 +1,29 @@
+test_lhbrx_1:
+  #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0
+  lhbrx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000200
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0
+
+test_lhbrx_2:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 01]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 2
+  lhbrx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000000000CD
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 2
+
+test_lhbrx_3:
+  #_ MEMORY_IN 0x0000000010001000 [FF, FE, FD, FC]
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x0000000010001000
+  lhbrx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000F00
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x0000000010001000

src/xenia/cpu/ppc/testing/instr_lhz.s

@@ -0,0 +1,43 @@
+test_lhz_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lhz r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x000000000000000B
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lhz_offset:
+  #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lhz r3, 4(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000003300
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lhzu_1:
+  #_ MEMORY_IN 0x0000000010001000 [AA, BB, CC, DD, EE, FF, 00, 11]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lhzu r3, 4(r4)
+  blr
+  #_ REGISTER_OUT r3 0x000000000000CC00
+  #_ REGISTER_OUT r4 0x0000000010001004
+
+test_lhzx_1:
+  #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 9A, BC, DE, F0]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000002
+  lhzx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000003400
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000002
+
+test_lhzux_1:
+  #_ MEMORY_IN 0x0000000010001000 [FF, EE, DD, CC, BB, AA, 99, 88]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000006
+  lhzux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000000000CC00
+  #_ REGISTER_OUT r4 0x0000000010001006
+  #_ REGISTER_OUT r5 0x0000000000000006

src/xenia/cpu/ppc/testing/instr_lhzu.s

@@ -0,0 +1,35 @@
+test_lhzu_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, 00, 00, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lhzu r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x000000000000000B
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lhzu_2:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 12, 34, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lhzu r3, 4(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001004
+
+test_lhzux_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 56, 78]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000006
+  lhzux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001006
+  #_ REGISTER_OUT r5 0x0000000000000006
+
+test_lhzux_2:
+  #_ MEMORY_IN 0x0000000010001000 [9A, BC, 00, 00, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  lhzux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000000000000A
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000000

src/xenia/cpu/ppc/testing/instr_lmw.s

@@ -0,0 +1,23 @@
+test_lmw_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 01, 00, 00, 00, 02, 00, 00, 00, 03]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r30 0
+  #_ REGISTER_IN r31 0
+  lmw r30, 0(r4)
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r30 0x0000000000000000
+  #_ REGISTER_OUT r31 0x0000000000000100
+
+test_lmw_2:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 0A, 00, 00, 00, 0B, 00, 00, 00, 0C, 00, 00, 00, 0D]
+  #_ REGISTER_IN r4 0x0000000010000FF8
+  #_ REGISTER_IN r29 0
+  #_ REGISTER_IN r30 0
+  #_ REGISTER_IN r31 0
+  lmw r29, 8(r4)
+  blr
+  #_ REGISTER_OUT r4 0x0000000010000FF8
+  #_ REGISTER_OUT r29 0x0000000000000000
+  #_ REGISTER_OUT r30 0x0000000000000A00
+  #_ REGISTER_OUT r31 0x0000000000000000

src/xenia/cpu/ppc/testing/instr_lvlx128.s

@@ -0,0 +1,18 @@
+test_lvlx128_1:
+  # Load vector left - loads from EA to high bytes
+  # EA=0x10001077, aligns to 0x10001070, offset=7
+  #_ MEMORY_IN 0x0000000010001070 [00, 00, 00, 00, 00, 00, 00, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12]
+  #_ REGISTER_IN r4 0x0000000010001077
+  lvlx128 v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001077
+  #_ REGISTER_OUT v3 [00000000, 0000000A, 00000000, 00000000]
+
+test_lvlx128_2:
+  # Test aligned address
+  #_ MEMORY_IN 0x0000000010001000 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, FA, FB, FC, FD, FE, FF]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lvlx128 v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT v3 [0000F100, F200F300, F400F500, F600F700]

src/xenia/cpu/ppc/testing/instr_lvlxl128.s

@@ -0,0 +1,9 @@
+test_lvlxl128_1:
+  # Load vector left with cache hint
+  # EA=0x10001077, aligns to 0x10001070, offset=7
+  #_ MEMORY_IN 0x0000000010001070 [00, 00, 00, 00, 00, 00, 00, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12]
+  #_ REGISTER_IN r4 0x0000000010001077
+  lvlxl128 v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001077
+  #_ REGISTER_OUT v3 [00000000, 0000000A, 00000000, 00000000]

src/xenia/cpu/ppc/testing/instr_lvrx128.s

@@ -0,0 +1,18 @@
+test_lvrx128_1:
+  # Load vector right - loads from EA to low bytes
+  # EA=0x10001077, aligns to 0x10001070, offset=7
+  #_ MEMORY_IN 0x0000000010001070 [00, 00, 00, 00, 00, 00, 00, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12]
+  #_ REGISTER_IN r4 0x0000000010001077
+  lvrx128 v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001077
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+
+test_lvrx128_2:
+  # Test aligned address
+  #_ MEMORY_IN 0x0000000010001000 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, FA, FB, FC, FD, FE, FF]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lvrx128 v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]

src/xenia/cpu/ppc/testing/instr_lvrxl128.s

@@ -0,0 +1,9 @@
+test_lvrxl128_1:
+  # Load vector right with cache hint
+  # EA=0x10001077, aligns to 0x10001070, offset=7
+  #_ MEMORY_IN 0x0000000010001070 [00, 00, 00, 00, 00, 00, 00, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12]
+  #_ REGISTER_IN r4 0x0000000010001077
+  lvrxl128 v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001077
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]

src/xenia/cpu/ppc/testing/instr_lvsl128.s

@@ -0,0 +1,20 @@
+test_lvsl128_1:
+  #_ REGISTER_IN r4 0x1070
+  lvsl128 v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1070
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvsl128_2:
+  #_ REGISTER_IN r4 0x1071
+  lvsl128 v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1071
+  #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
+
+test_lvsl128_3:
+  #_ REGISTER_IN r4 0x107F
+  lvsl128 v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x107F
+  #_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E]

src/xenia/cpu/ppc/testing/instr_lvsr128.s

@@ -0,0 +1,20 @@
+test_lvsr128_1:
+  #_ REGISTER_IN r4 0x1070
+  lvsr128 v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1070
+  #_ REGISTER_OUT v3 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+
+test_lvsr128_2:
+  #_ REGISTER_IN r4 0x1071
+  lvsr128 v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1071
+  #_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E]
+
+test_lvsr128_3:
+  #_ REGISTER_IN r4 0x107F
+  lvsr128 v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x107F
+  #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]

src/xenia/cpu/ppc/testing/instr_lvxl128.s

@@ -0,0 +1,22 @@
+test_lvxl128_1:
+  # Basic 128-bit aligned load with cache hint
+  #_ MEMORY_IN 0x0000000010001000 [01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10]
+  #_ REGISTER_IN r4 0x0000000010001000
+  li r5, 0
+  lvxl128 v3, r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT v3 [00010200, 03000400, 05000600, 07000800]
+
+test_lvxl128_2:
+  # Test with offset
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00]
+  #_ MEMORY_IN 0x0000000010001010 [AA, BB, CC, DD, EE, FF, 00, 11, 22, 33, 44, 55, 66, 77, 88, 99]
+  #_ REGISTER_IN r4 0x0000000010001000
+  li r5, 16
+  lvxl128 v3, r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 16
+  #_ REGISTER_OUT v3 [000ABB00, CC00DD00, EE00FF00, 00001100]

src/xenia/cpu/ppc/testing/instr_lwa.s

@@ -0,0 +1,45 @@
+test_lwa_positive:
+  #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 7F, FF, FF, FF]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lwa r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000023400
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lwa_negative:
+  #_ MEMORY_IN 0x0000000010001000 [FF, FF, FF, FF, 80, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lwa r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x00000000000FFF00
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lwax_positive:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 01, 11, 22, 33, 44]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000004
+  lwax r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000004
+
+test_lwax_negative:
+  #_ MEMORY_IN 0x0000000010001000 [80, 00, 00, 01, AA, BB, CC, DD]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  lwax r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000000
+
+test_lwaux_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, FE, DC, BA, 98]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000008
+  lwaux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001008
+  #_ REGISTER_OUT r5 0x0000000000000008

src/xenia/cpu/ppc/testing/instr_lwbrx.s

@@ -0,0 +1,29 @@
+test_lwbrx_1:
+  #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 9A, BC, DE, F0]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0
+  lwbrx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000340200
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0
+
+test_lwbrx_2:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 01, 23, 45, 67, 89]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 4
+  lwbrx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000000100EF
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 4
+
+test_lwbrx_3:
+  #_ MEMORY_IN 0x0000000010001000 [FF, FE, FD, FC, FB, FA, F9, F8]
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x0000000010001000
+  lwbrx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000FE0F00
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x0000000010001000

src/xenia/cpu/ppc/testing/instr_lwz.s

@@ -0,0 +1,43 @@
+test_lwz_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lwz r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x00000000000BCD00
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lwz_offset:
+  #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lwz r3, 4(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000033004400
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lwzu_1:
+  #_ MEMORY_IN 0x0000000010001000 [AA, BB, CC, DD, EE, FF, 00, 11]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lwzu r3, 4(r4)
+  blr
+  #_ REGISTER_OUT r3 0x00000000CC00DD00
+  #_ REGISTER_OUT r4 0x0000000010001004
+
+test_lwzx_1:
+  #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 9A, BC, DE, F0]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000004
+  lwzx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000056007800
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000004
+
+test_lwzux_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, FF, EE, DD, CC]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000008
+  lwzux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001008
+  #_ REGISTER_OUT r5 0x0000000000000008

src/xenia/cpu/ppc/testing/instr_lwzu.s

@@ -0,0 +1,35 @@
+test_lwzu_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lwzu r3, 0(r4)
+  blr
+  #_ REGISTER_OUT r3 0x00000000000BCD00
+  #_ REGISTER_OUT r4 0x0000000010001000
+
+test_lwzu_2:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 12, 34, 56, 78]
+  #_ REGISTER_IN r4 0x0000000010001000
+  lwzu r3, 4(r4)
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001004
+
+test_lwzux_1:
+  #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 9A, BC, DE, F0]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000006
+  lwzux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000010001006
+  #_ REGISTER_OUT r5 0x0000000000000006
+
+test_lwzux_2:
+  #_ MEMORY_IN 0x0000000010001000 [FE, DC, BA, 98, 00, 00, 00, 00]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  lwzux r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000000EDC00
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000000

src/xenia/cpu/ppc/testing/instr_lxarx.s

@@ -0,0 +1,39 @@
+test_lwarx_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  lwarx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000000BCD00
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000000
+
+test_lwarx_offset:
+  #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000004
+  lwarx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000033004400
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000004
+
+test_ldarx_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  ldarx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000BCD00EF001200
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000000
+
+test_ldarx_offset:
+  #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000004
+  ldarx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x3300440055006600
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000004

src/xenia/cpu/ppc/testing/instr_lxbrx.s

@@ -0,0 +1,59 @@
+test_lhbrx_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  lhbrx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000B00
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000000
+
+test_lhbrx_offset:
+  #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000004
+  lhbrx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000033
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000004
+
+test_lwbrx_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  lwbrx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000CD0B00
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000000
+
+test_lwbrx_offset:
+  #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000004
+  lwbrx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000440033
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000004
+
+test_ldbrx_1:
+  #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  ldbrx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x001200EF00CD0B00
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000000
+
+test_ldbrx_offset:
+  #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88, 99, AA, BB, CC]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0x0000000000000004
+  ldbrx r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0066005500440033
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0x0000000000000004

src/xenia/cpu/ppc/testing/instr_mcrfs.s

@@ -0,0 +1,19 @@
+test_mcrfs_1:
+  #_ REGISTER_IN f1 1.0
+  #_ REGISTER_IN f2 2.0
+  fadds f3, f1, f2
+  mcrfs 1, 0
+  blr
+  #_ REGISTER_OUT f1 1.0
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 3.0
+
+test_mcrfs_2:
+  #_ REGISTER_IN f1 0x7FF0000000000001
+  #_ REGISTER_IN f2 1.0
+  fadd f3, f1, f2
+  mcrfs 2, 0
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000001
+  #_ REGISTER_OUT f2 1.0
+  #_ REGISTER_OUT f3 0x7FF8000000000001

src/xenia/cpu/ppc/testing/instr_mcrxr.s

@@ -0,0 +1,19 @@
+test_mcrxr_1:
+  #_ REGISTER_IN r3 0x0000000000000001
+  #_ REGISTER_IN r4 0x0000000000000001
+  addc r5, r3, r4
+  mcrxr 1
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000000001
+  #_ REGISTER_OUT r5 0x0000000000000002
+
+test_mcrxr_2:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0000000000000001
+  addc r5, r3, r4
+  mcrxr 2
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0000000000000001
+  #_ REGISTER_OUT r5 0x0000000000000000

src/xenia/cpu/ppc/testing/instr_mffsx.s

@@ -0,0 +1,31 @@
+test_mffsx_1:
+  #_ REGISTER_IN f1 [0000000000000000]
+  mtfsf 0xFF, f1
+  mffs. f3
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f1 [0000000000000000]
+
+test_mffsx_2:
+  #_ REGISTER_IN f1 [0000000000000005]
+  mtfsf 0xFF, f1
+  mffs. f4
+  blr
+  #_ REGISTER_OUT f4 [0000000000000005]
+  #_ REGISTER_OUT f1 [0000000000000005]
+
+test_mffsx_3:
+  #_ REGISTER_IN f1 [00000000000000F0]
+  mtfsf 0xFF, f1
+  mffs. f5
+  blr
+  #_ REGISTER_OUT f5 [00000000000000F0]
+  #_ REGISTER_OUT f1 [00000000000000F0]
+
+test_mffsx_4:
+  #_ REGISTER_IN f1 [0000000012345678]
+  mtfsf 0xFF, f1
+  mffs. f6
+  blr
+  #_ REGISTER_OUT f6 [0000000012345678]
+  #_ REGISTER_OUT f1 [0000000012345678]

src/xenia/cpu/ppc/testing/instr_mfmsr.s

@@ -0,0 +1,11 @@
+test_mfmsr_1:
+  #_ REGISTER_IN r3 0x0000000000000000
+  mfmsr r3
+  blr
+  #_ REGISTER_OUT r3 0x0000000000009030
+
+test_mfmsr_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  mfmsr r4
+  blr
+  #_ REGISTER_OUT r4 0x0000000000009030

src/xenia/cpu/ppc/testing/instr_mfspr.s

@@ -0,0 +1,28 @@
+test_mfspr_xer:
+  #_ REGISTER_IN r3 0x0000000000000001
+  #_ REGISTER_IN r4 0x0000000000000001
+  addc r5, r3, r4
+  mfspr r6, xer
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000000001
+  #_ REGISTER_OUT r5 0x0000000000000002
+  #_ REGISTER_OUT r6 0x0000000000000000
+
+test_mfspr_lr:
+  #_ REGISTER_IN r3 0x0000000012345678
+  mflr r5
+  mtlr r3
+  mfspr r4, lr
+  mtlr r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000012345678
+  #_ REGISTER_OUT r4 0x0000000012345678
+
+test_mfspr_ctr:
+  #_ REGISTER_IN r3 0x00000000ABCDEF01
+  mtctr r3
+  mfspr r4, ctr
+  blr
+  #_ REGISTER_OUT r3 0x00000000ABCDEF01
+  #_ REGISTER_OUT r4 0x00000000ABCDEF01

src/xenia/cpu/ppc/testing/instr_mftb.s

@@ -0,0 +1,26 @@
+test_mftb_1:
+  #_ REGISTER_IN r3 0x0000000000000000
+  #_ REGISTER_IN r4 0x0000000000000000
+  #_ REGISTER_IN r5 0x0000000000000000
+  mftb r3, 268
+  mftb r4, 268
+  cmpd r4, r3
+  li r5, 0
+  bgt .+8
+  b .+8
+  li r5, 1
+  blr
+  #_ REGISTER_OUT r5 0x0000000000000001
+
+test_mftb_2:
+  #_ REGISTER_IN r3 0x0000000000000000
+  #_ REGISTER_IN r4 0x0000000000000000
+  #_ REGISTER_IN r5 0x0000000000000000
+  mftb r3, 269
+  mftb r4, 269
+  cmpd r4, r3
+  li r5, 0
+  blt .+8
+  li r5, 1
+  blr
+  #_ REGISTER_OUT r5 0x0000000000000001

src/xenia/cpu/ppc/testing/instr_mfvscr.s

@@ -0,0 +1,11 @@
+test_mfvscr_1:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  mfvscr v3
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00010000]
+
+test_mtvscr_1:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00010001]
+  mtvscr v3
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00010001]

src/xenia/cpu/ppc/testing/instr_mtcrf.s

@@ -0,0 +1,23 @@
+test_mtcrf_1:
+  #_ REGISTER_IN r3 0x0000000012345678
+  mtcrf 0xFF, r3
+  mfcr r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000012345678
+  #_ REGISTER_OUT r4 0x0000000012345678
+
+test_mtcrf_2:
+  #_ REGISTER_IN r3 0x00000000ABCDEF01
+  mtcrf 0x0F, r3
+  mfcr r4
+  blr
+  #_ REGISTER_OUT r3 0x00000000ABCDEF01
+  #_ REGISTER_OUT r4 0x000000000000EF01
+
+test_mtcrf_3:
+  #_ REGISTER_IN r3 0x00000000F0F0F0F0
+  mtcrf 0xAA, r3
+  mfcr r4
+  blr
+  #_ REGISTER_OUT r3 0x00000000F0F0F0F0
+  #_ REGISTER_OUT r4 0x00000000F0F0F0F0

src/xenia/cpu/ppc/testing/instr_mtfsfix.s

@@ -0,0 +1,15 @@
+test_mtfsfix_1:
+  mtfsfi. 0, 0
+  blr
+
+test_mtfsfix_2:
+  mtfsfi. 1, 1
+  blr
+
+test_mtfsfix_3:
+  mtfsfi. 7, 15
+  blr
+
+test_mtfsfix_4:
+  mtfsfi. 0, 7
+  blr

src/xenia/cpu/ppc/testing/instr_mtfsfx.s

@@ -0,0 +1,23 @@
+test_mtfsfx_1:
+  #_ REGISTER_IN f1 [0000000000000001]
+  mtfsf. 0xFF, f1
+  blr
+  #_ REGISTER_OUT f1 [0000000000000001]
+
+test_mtfsfx_2:
+  #_ REGISTER_IN f1 [0000000000000000]
+  mtfsf. 0xFF, f1
+  blr
+  #_ REGISTER_OUT f1 [0000000000000000]
+
+test_mtfsfx_3:
+  #_ REGISTER_IN f1 [0000000000000007]
+  mtfsf. 0xFF, f1
+  blr
+  #_ REGISTER_OUT f1 [0000000000000007]
+
+test_mtfsfx_4:
+  #_ REGISTER_IN f1 [00000000000000FF]
+  mtfsf. 0xFF, f1
+  blr
+  #_ REGISTER_OUT f1 [00000000000000FF]

src/xenia/cpu/ppc/testing/instr_mtmsr.s

@@ -0,0 +1,11 @@
+test_mtmsr_1:
+  #_ REGISTER_IN r3 0x0000000000000000
+  mtmsr r3
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+
+test_mtmsr_2:
+  #_ REGISTER_IN r4 0x0000000000001234
+  mtmsr r4
+  blr
+  #_ REGISTER_OUT r4 0x0000000000001234

src/xenia/cpu/ppc/testing/instr_mtmsrd.s

@@ -0,0 +1,11 @@
+test_mtmsrd_1:
+  #_ REGISTER_IN r3 0x0000000000000000
+  mtmsrd r3
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+
+test_mtmsrd_2:
+  #_ REGISTER_IN r4 0x0000000000001234
+  mtmsrd r4
+  blr
+  #_ REGISTER_OUT r4 0x0000000000001234

src/xenia/cpu/ppc/testing/instr_mtspr.s

@@ -0,0 +1,25 @@
+test_mtspr_xer:
+  #_ REGISTER_IN r3 0x0000000020000000
+  mtspr xer, r3
+  mfspr r4, xer
+  blr
+  #_ REGISTER_OUT r3 0x0000000020000000
+  #_ REGISTER_OUT r4 0x0000000020000000
+
+test_mtspr_lr:
+  #_ REGISTER_IN r3 0x0000000012345678
+  mflr r5
+  mtspr lr, r3
+  mflr r4
+  mtlr r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000012345678
+  #_ REGISTER_OUT r4 0x0000000012345678
+
+test_mtspr_ctr:
+  #_ REGISTER_IN r3 0x00000000ABCDEF01
+  mtspr ctr, r3
+  mfctr r4
+  blr
+  #_ REGISTER_OUT r3 0x00000000ABCDEF01
+  #_ REGISTER_OUT r4 0x00000000ABCDEF01

src/xenia/cpu/ppc/testing/instr_mulhdux.s

@@ -0,0 +1,35 @@
+test_mulhdux_1:
+  #_ REGISTER_IN r4 0x0000000100000000
+  #_ REGISTER_IN r5 0x0000000100000000
+  mulhdu. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000100000000
+  #_ REGISTER_OUT r5 0x0000000100000000
+
+test_mulhdux_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000002
+  mulhdu. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0x0000000000000002
+
+test_mulhdux_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  mulhdu. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_mulhdux_4:
+  #_ REGISTER_IN r4 0x0000000000000001
+  #_ REGISTER_IN r5 0x0000000000000001
+  mulhdu. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000000000001
+  #_ REGISTER_OUT r5 0x0000000000000001

src/xenia/cpu/ppc/testing/instr_mulhdx.s

@@ -0,0 +1,82 @@
+test_mulhdx_1:
+  #_ REGISTER_IN r4 0x0000000100000000
+  #_ REGISTER_IN r5 0x0000000100000000
+  mulhd. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_mulhdx_1_constant:
+  lis r4, 0x0001
+  sldi r4, r4, 32
+  lis r5, 0x0001
+  sldi r5, r5, 32
+  mulhd. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r12 0x0000000020000000
+
+test_mulhdx_negative:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000002
+  mulhd. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r12 0x0000000080000000
+
+test_mulhdx_max:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  mulhd. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r12 0x0000000020000000
+
+test_mulhdux_1:
+  #_ REGISTER_IN r4 0x0000000100000000
+  #_ REGISTER_IN r5 0x0000000100000000
+  mulhdu. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_mulhdux_max:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  mulhdu. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r12 0x0000000080000000
+
+test_mulhwx_1:
+  #_ REGISTER_IN r4 0x0000000000010000
+  #_ REGISTER_IN r5 0x0000000000010000
+  mulhw. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_mulhwux_1:
+  #_ REGISTER_IN r4 0x0000000000010000
+  #_ REGISTER_IN r5 0x0000000000010000
+  mulhwu. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_mulhwux_max:
+  #_ REGISTER_IN r4 0x00000000FFFFFFFF
+  #_ REGISTER_IN r5 0x00000000FFFFFFFF
+  mulhwu. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFE
+  #_ REGISTER_OUT r12 0x0000000080000000

src/xenia/cpu/ppc/testing/instr_mulhwux.s

@@ -0,0 +1,35 @@
+test_mulhwux_1:
+  #_ REGISTER_IN r4 0x0000000000010000
+  #_ REGISTER_IN r5 0x0000000000010000
+  mulhwu. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000010000
+  #_ REGISTER_OUT r5 0x0000000000010000
+
+test_mulhwux_2:
+  #_ REGISTER_IN r4 0x00000000FFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000002
+  mulhwu. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r5 0x0000000000000002
+
+test_mulhwux_3:
+  #_ REGISTER_IN r4 0x00000000FFFFFFFF
+  #_ REGISTER_IN r5 0x00000000FFFFFFFF
+  mulhwu. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFE
+  #_ REGISTER_OUT r4 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r5 0x00000000FFFFFFFF
+
+test_mulhwux_4:
+  #_ REGISTER_IN r4 0x0000000000000001
+  #_ REGISTER_IN r5 0x0000000000000001
+  mulhwu. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000000000001
+  #_ REGISTER_OUT r5 0x0000000000000001

src/xenia/cpu/ppc/testing/instr_mulhwx.s

@@ -0,0 +1,35 @@
+test_mulhwx_1:
+  #_ REGISTER_IN r4 0x0000000000010000
+  #_ REGISTER_IN r5 0x0000000000010000
+  mulhw. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000010000
+  #_ REGISTER_OUT r5 0x0000000000010000
+
+test_mulhwx_2:
+  #_ REGISTER_IN r4 0x00000000FFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000002
+  mulhw. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r5 0x0000000000000002
+
+test_mulhwx_3:
+  #_ REGISTER_IN r4 0x0000000080000000
+  #_ REGISTER_IN r5 0x0000000000000002
+  mulhw. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0000000080000000
+  #_ REGISTER_OUT r5 0x0000000000000002
+
+test_mulhwx_4:
+  #_ REGISTER_IN r4 0x0000000000000001
+  #_ REGISTER_IN r5 0x0000000000000001
+  mulhw. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000000000001
+  #_ REGISTER_OUT r5 0x0000000000000001

src/xenia/cpu/ppc/testing/instr_mulldx.s

@@ -0,0 +1,53 @@
+test_mulldx_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000000010
+  mulld. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000010000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_mulldx_1_constant:
+  li r4, 0x1000
+  li r5, 0x10
+  mulld. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000010000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_mulldx_negative:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000002
+  mulld. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r12 0x0000000080000000
+
+test_mulldx_overflow:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  mulld. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_mullwx_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000000010
+  mullw. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000010000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_mullwx_negative:
+  #_ REGISTER_IN r4 0x00000000FFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000002
+  mullw. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r12 0x0000000080000000

src/xenia/cpu/ppc/testing/instr_negx.s

@@ -0,0 +1,39 @@
+test_negx_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  neg. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFF000
+  #_ REGISTER_OUT r12 0x0000000080000000
+
+test_negx_1_constant:
+  li r4, 0x1000
+  neg. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFF000
+  #_ REGISTER_OUT r12 0x0000000080000000
+
+test_negx_negative:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  neg. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_negx_zero:
+  #_ REGISTER_IN r4 0x0000000000000000
+  neg. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r12 0x0000000020000000
+
+test_negx_min:
+  #_ REGISTER_IN r4 0x8000000000000000
+  neg. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+  #_ REGISTER_OUT r12 0x0000000020000000

src/xenia/cpu/ppc/testing/instr_orcx.s

@@ -0,0 +1,35 @@
+test_orcx_1:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xAAAAAAAAAAAAAAAA
+  orc. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xAAAAAAAAAAAAAAAA
+
+test_orcx_2:
+  #_ REGISTER_IN r4 0xAAAAAAAAAAAAAAAA
+  #_ REGISTER_IN r5 0x5555555555555555
+  orc. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xAAAAAAAAAAAAAAAA
+  #_ REGISTER_OUT r4 0xAAAAAAAAAAAAAAAA
+  #_ REGISTER_OUT r5 0x5555555555555555
+
+test_orcx_3:
+  #_ REGISTER_IN r4 0x0000000000000000
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  orc. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000000000000
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_orcx_4:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  #_ REGISTER_IN r5 0x0F0F0F0F0F0F0F0F
+  orc. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xF2F4F6F8FAFCFEF0
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x0F0F0F0F0F0F0F0F

src/xenia/cpu/ppc/testing/instr_rldclx.s

@@ -0,0 +1,35 @@
+test_rldclx_1:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  #_ REGISTER_IN r5 0x0000000000000008
+  rldcl. r3, r4, r5, 56
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000012
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x0000000000000008
+
+test_rldclx_2:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  #_ REGISTER_IN r5 0x0000000000000010
+  rldcl. r3, r4, r5, 48
+  blr
+  #_ REGISTER_OUT r3 0x0000000000001234
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x0000000000000010
+
+test_rldclx_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000000
+  rldcl. r3, r4, r5, 32
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0x0000000000000000
+
+test_rldclx_4:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  #_ REGISTER_IN r5 0x0000000000000020
+  rldcl. r3, r4, r5, 32
+  blr
+  #_ REGISTER_OUT r3 0x0000000012345678
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x0000000000000020

src/xenia/cpu/ppc/testing/instr_rldcrx.s

@@ -0,0 +1,35 @@
+test_rldcrx_1:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  #_ REGISTER_IN r5 0x0000000000000008
+  rldcr. r3, r4, r5, 55
+  blr
+  #_ REGISTER_OUT r3 0x3456789ABCDEF000
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x0000000000000008
+
+test_rldcrx_2:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  #_ REGISTER_IN r5 0x0000000000000010
+  rldcr. r3, r4, r5, 47
+  blr
+  #_ REGISTER_OUT r3 0x56789ABCDEF00000
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x0000000000000010
+
+test_rldcrx_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000000
+  rldcr. r3, r4, r5, 31
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF00000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0x0000000000000000
+
+test_rldcrx_4:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  #_ REGISTER_IN r5 0x0000000000000020
+  rldcr. r3, r4, r5, 31
+  blr
+  #_ REGISTER_OUT r3 0x9ABCDEF000000000
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x0000000000000020

src/xenia/cpu/ppc/testing/instr_rldiclx.s

@@ -0,0 +1,27 @@
+test_rldiclx_1:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  rldicl. r3, r4, 8, 56
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000012
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+
+test_rldiclx_2:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  rldicl. r3, r4, 16, 48
+  blr
+  #_ REGISTER_OUT r3 0x0000000000001234
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+
+test_rldiclx_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  rldicl. r3, r4, 0, 32
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_rldiclx_4:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  rldicl. r3, r4, 32, 32
+  blr
+  #_ REGISTER_OUT r3 0x0000000012345678
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0

src/xenia/cpu/ppc/testing/instr_rldicrx.s

@@ -0,0 +1,27 @@
+test_rldicrx_1:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  rldicr. r3, r4, 8, 55
+  blr
+  #_ REGISTER_OUT r3 0x3456789ABCDEF000
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+
+test_rldicrx_2:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  rldicr. r3, r4, 16, 47
+  blr
+  #_ REGISTER_OUT r3 0x56789ABCDEF00000
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+
+test_rldicrx_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  rldicr. r3, r4, 0, 31
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF00000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_rldicrx_4:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  rldicr. r3, r4, 32, 31
+  blr
+  #_ REGISTER_OUT r3 0x9ABCDEF000000000
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0

src/xenia/cpu/ppc/testing/instr_rldicx.s

@@ -0,0 +1,27 @@
+test_rldicx_1:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  rldic. r3, r4, 8, 48
+  blr
+  #_ REGISTER_OUT r3 0x000000000000F000
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+
+test_rldicx_2:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  rldic. r3, r4, 16, 40
+  blr
+  #_ REGISTER_OUT r3 0x0000000000F00000
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+
+test_rldicx_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  rldic. r3, r4, 4, 56
+  blr
+  #_ REGISTER_OUT r3 0x00000000000000F0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_rldicx_4:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  rldic. r3, r4, 0, 0
+  blr
+  #_ REGISTER_OUT r3 0x123456789ABCDEF0
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0