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[Testing] Add a lot more missing instruction tests

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Herman S.
2025-10-19 13:42:59 +09:00
parent 9e9b733dfb
commit 1b25574986
166 changed files with 5621 additions and 0 deletions
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src/xenia/cpu/ppc/testing/instr_stvlxl128.s Normal file
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test_stvlxl128_1:
# Store vector left 128 with cache hint
# EA=0x10001077, aligns to 0x10001070, offset=7
#_ MEMORY_IN 0x0000000010001070 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC]
#_ REGISTER_IN r4 0x0000000010001077
#_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
stvlxl128 v3, r4, r0
blr
#_ REGISTER_OUT r4 0x0000000010001077
#_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
#_ MEMORY_OUT 10001077 010203040506070809
test_stvlxl128_2:
# Test aligned address
#_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC]
#_ REGISTER_IN r4 0x0000000010001000
#_ REGISTER_IN v3 [AABBCCDD, EEFF0011, 22334455, 66778899]
stvlxl128 v3, r4, r0
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT v3 [AABBCCDD, EEFF0011, 22334455, 66778899]
#_ MEMORY_OUT 10001000 AABBCCDDEEFF00112233445566778899