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[Testing] Add a lot more missing instruction tests

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Herman S.
2025-10-19 13:42:59 +09:00
parent 9e9b733dfb
commit 1b25574986
166 changed files with 5621 additions and 0 deletions
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8
src/xenia/cpu/ppc/testing/instr_vsraw128.s Normal file
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test_vsraw128_1:
#_ REGISTER_IN v3 [80000000, 00000100, FFFFFFF0, 00000008]
#_ REGISTER_IN v4 [00000001, 00000002, 00000003, 00000004]
vsraw128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [80000000, 00000100, FFFFFFF0, 00000008]
#_ REGISTER_OUT v4 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_OUT v5 [C0000000, 00000040, FFFFFFFE, 00000000]