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[Testing] Add some lvx* tests

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This commit is contained in:
Herman S.
2025-10-18 11:32:13 +09:00
parent 32b0e2c323
commit 4832bb485f
4 changed files with 415 additions and 0 deletions
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116
src/xenia/cpu/ppc/testing/instr_lvx.s Normal file
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test_lvx_1:
#_ MEMORY_IN 0x0000000010001000 [01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
lvx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT v3 [00010200, 03000400, 05000600, 07000800]
test_lvx_2:
# Test with base+offset addressing
#_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, AA, BB, CC, DD, EE, FF, 11, 22]
#_ MEMORY_IN 0x0000000010001010 [33, 44, 55, 66, 77, 88, 99, 00, 11, 22, 33, 44, 55, 66, 77, 88]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 16
lvx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 16
#_ REGISTER_OUT v3 [00034400, 55006600, 77008800, 99000000]
test_lvx_3:
# Test unaligned address (should mask to 16-byte boundary)
#_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88, 99, AA, BB, CC, DD, EE, FF, 00]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 5 # unaligned offset
lvx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 5
# Should load from aligned address 0x10001000 (masks low 4 bits)
#_ REGISTER_OUT v3 [00012200, 33004400, 55006600, 77008800]
test_lvx_4:
# Test with zero base register
#_ MEMORY_IN 0x0000000010001000 [FF, EE, DD, CC, BB, AA, 99, 88, 77, 66, 55, 44, 33, 22, 11, 00]
#_ REGISTER_IN r4 0
lis r5, 0x1000
addi r5, r5, 0x1000
lvx v3, r4, r5
blr
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 0x10001000
#_ REGISTER_OUT v3 [000FEE00, DD00CC00, BB00AA00, 99008800]
test_lvx_5:
# Test loading all zeros
#_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
lvx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_lvx_6:
# Test loading all ones
#_ MEMORY_IN 0x0000000010001000 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
lvx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT v3 [000FFF00, FF00FF00, FF00FF00, FF00FF00]
test_lvx_7:
# Test loading pattern data
#_ MEMORY_IN 0x0000000010001000 [01, 23, 45, 67, 89, AB, CD, EF, FE, DC, BA, 98, 76, 54, 32, 10]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
lvx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT v3 [00012300, 45006700, 8900AB00, CD00EF00]
test_lvx_8:
# Test multiple loads to different registers
#_ MEMORY_IN 0x0000000010001000 [11, 11, 11, 11, 22, 22, 22, 22, 33, 33, 33, 33, 44, 44, 44, 44]
#_ MEMORY_IN 0x0000000010001010 [55, 55, 55, 55, 66, 66, 66, 66, 77, 77, 77, 77, 88, 88, 88, 88]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
lvx v3, r4, r5
li r5, 16
lvx v4, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 16
#_ REGISTER_OUT v3 [00011100, 11001100, 22002200, 22002200]
#_ REGISTER_OUT v4 [00055500, 55005500, 66006600, 66006600]
test_lvx_9:
# Test unaligned address with larger offset (should mask to 16-byte boundary)
#_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00]
#_ MEMORY_IN 0x0000000010001010 [AA, BB, CC, DD, EE, FF, 11, 22, 33, 44, 55, 66, 77, 88, 99, 00]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 23 # unaligned: should load from 0x10001010 (aligned)
lvx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 23
#_ REGISTER_OUT v3 [000ABB00, CC00DD00, EE00FF00, 11002200]
test_lvx_10:
# Test with high address
#_ MEMORY_IN 0x0000000010001000 [DE, AD, BE, EF, CA, FE, BA, BE, 12, 34, 56, 78, 9A, BC, DE, F0]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
lvx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT v3 [000EAD00, BE00EF00, CA00FE00, BA00BE00]

96
src/xenia/cpu/ppc/testing/instr_lvx128.s Normal file
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test_lvx128_1:
# Basic 128-bit aligned load
#_ MEMORY_IN 0x0000000010001000 [01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
# lvx128 v3, r4, r5
.long 0x106428C3 # lvx128 v3, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT v3 [00010200, 03000400, 05000600, 07000800]
test_lvx128_2:
# Test with offset
#_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00]
#_ MEMORY_IN 0x0000000010001010 [AA, BB, CC, DD, EE, FF, 00, 11, 22, 33, 44, 55, 66, 77, 88, 99]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 16
# lvx128 v3, r4, r5
.long 0x106428C3
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 16
#_ REGISTER_OUT v3 [000ABB00, CC00DD00, EE00FF00, 00001100]
test_lvx128_3:
# Test unaligned address (should mask to 16-byte boundary)
#_ MEMORY_IN 0x0000000010001000 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, FA, FB, FC, FD, FE, FF]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 13 # unaligned
# lvx128 v3, r4, r5
.long 0x106428C3
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 13
# Should load from aligned address 0x10001000
#_ REGISTER_OUT v3 [0000F100, F200F300, F400F500, F600F700]
test_lvx128_4:
# Test with large offset
#_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00]
#_ MEMORY_IN 0x0000000010001010 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00]
#_ MEMORY_IN 0x0000000010001020 [DE, AD, BE, EF, CA, FE, BA, BE, 00, 11, 22, 33, 44, 55, 66, 77]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 32
# lvx128 v3, r4, r5
.long 0x106428C3
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 32
#_ REGISTER_OUT v3 [000EAD00, BE00EF00, CA00FE00, BA00BE00]
test_lvx128_5:
# Test pattern data
#_ MEMORY_IN 0x0000000010001000 [00, 11, 22, 33, 44, 55, 66, 77, 88, 99, AA, BB, CC, DD, EE, FF]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
# lvx128 v3, r4, r5
.long 0x106428C3
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT v3 [00001100, 22003300, 44005500, 66007700]
test_lvx128_6:
# Test loading to high register (v100+)
#_ MEMORY_IN 0x0000000010001000 [A5, A5, A5, A5, 5A, 5A, 5A, 5A, FF, 00, FF, 00, 00, FF, 00, FF]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
# lvx128 v100, r4, r5
.long 0x1C8428C3 # lvx128 v100, r4, r5
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT v100 [00000000, 00000000, 00000000, 00000000]
test_lvx128_7:
# Load multiple vectors sequentially
#_ MEMORY_IN 0x0000000010001000 [11, 11, 11, 11, 22, 22, 22, 22, 33, 33, 33, 33, 44, 44, 44, 44]
#_ MEMORY_IN 0x0000000010001010 [55, 55, 55, 55, 66, 66, 66, 66, 77, 77, 77, 77, 88, 88, 88, 88]
#_ MEMORY_IN 0x0000000010001020 [99, 99, 99, 99, AA, AA, AA, AA, BB, BB, BB, BB, CC, CC, CC, CC]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
# lvx128 v3, r4, r5
.long 0x106428C3
li r5, 16
# lvx128 v4, r4, r5
.long 0x108428C3
li r5, 32
# lvx128 v5, r4, r5
.long 0x10A428C3
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 32
#_ REGISTER_OUT v3 [00011100, 11001100, 22002200, 22002200]
#_ REGISTER_OUT v4 [00055500, 55005500, 66006600, 66006600]
#_ REGISTER_OUT v5 [00099900, 99009900, AA00AA00, AA00AA00]

125
src/xenia/cpu/ppc/testing/instr_lvx_permute.s Normal file
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test_lvx_vperm_1:
# Load two vectors and permute them
#_ MEMORY_IN 0x0000000010001000 [00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F]
#_ MEMORY_IN 0x0000000010001010 [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F]
#_ REGISTER_IN r4 0x0000000010001000
#_ REGISTER_IN v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
li r6, 0
lvx v3, r4, r6
li r6, 16
lvx v4, r4, r6
vperm v7, v3, v4, v5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r6 16
#_ REGISTER_OUT v3 [00000100, 02000300, 04000500, 06000700]
#_ REGISTER_OUT v4 [00001100, 12001300, 14001500, 16001700]
#_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v7 [00000100, 02000300, 04000500, 06000700]
test_lvx_vperm_2:
# Load and permute with byte reversal
#_ MEMORY_IN 0x0000000010001000 [00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F]
#_ MEMORY_IN 0x0000000010001010 [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F]
#_ REGISTER_IN r4 0x0000000010001000
#_ REGISTER_IN v5 [0F0E0D0C, 0B0A0908, 07060504, 03020100] # reverse control
li r6, 0
lvx v3, r4, r6
li r6, 16
lvx v4, r4, r6
vperm v7, v3, v4, v5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r6 16
#_ REGISTER_OUT v3 [00000100, 02000300, 04000500, 06000700]
#_ REGISTER_OUT v4 [00001100, 12001300, 14001500, 16001700]
#_ REGISTER_OUT v5 [0F0E0D0C, 0B0A0908, 07060504, 03020100]
#_ REGISTER_OUT v7 [00070006, 00050004, 00030002, 00010000]
test_lvx_vpermwi128_1:
# Load and swizzle words
#_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88, 99, AA, BB, CC, DD, EE, FF, 00]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
lvx v3, r4, r5
# vpermwi128 v4, v3, 0xE4 (reverse words: 3,2,1,0)
.long 0x18841BD0
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT v3 [00012200, 33004400, 55006600, 77008800]
#_ REGISTER_OUT v4 [77008800, 55006600, 33004400, 00012200]
test_lvx_vpermwi128_2:
# Load and broadcast first word
#_ MEMORY_IN 0x0000000010001000 [CA, FE, BA, BE, DE, AD, BE, EF, 12, 34, 56, 78, 9A, BC, DE, F0]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
lvx v3, r4, r5
# vpermwi128 v4, v3, 0 (broadcast word 0)
.long 0x18801A10
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT v3 [000AFE00, BA00BE00, DE00AD00, BE00EF00]
#_ REGISTER_OUT v4 [000AFE00, 000AFE00, 000AFE00, 000AFE00]
test_lvxl_vperm_1:
# Load with LRU hint and permute
#_ MEMORY_IN 0x0000000010001000 [AA, BB, CC, DD, EE, FF, 00, 11, 22, 33, 44, 55, 66, 77, 88, 99]
#_ MEMORY_IN 0x0000000010001010 [00, 11, 22, 33, 44, 55, 66, 77, 88, 99, AA, BB, CC, DD, EE, FF]
#_ REGISTER_IN r4 0x0000000010001000
#_ REGISTER_IN v5 [10111213, 14151617, 18191A1B, 1C1D1E1F] # select from second vector
li r6, 0
lvxl v3, r4, r6
li r6, 16
lvxl v4, r4, r6
vperm v7, v3, v4, v5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r6 16
#_ REGISTER_OUT v3 [000ABB00, CC00DD00, EE00FF00, 00001100]
#_ REGISTER_OUT v4 [00001100, 22003300, 44005500, 66007700]
#_ REGISTER_OUT v5 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v7 [00001100, 22003300, 44005500, 66007700]
test_lvx128_vperm_1:
# Load 128-bit vector and permute with itself
#_ MEMORY_IN 0x0000000010001000 [01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10]
#_ REGISTER_IN r4 0x0000000010001000
#_ REGISTER_IN v5 [03020100, 07060504, 0B0A0908, 0F0E0D0C] # reverse bytes
li r6, 0
# lvx128 v3, r4, r6
.long 0x106430C3
vperm v7, v3, v3, v5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT v3 [00010200, 03000400, 05000600, 07000800]
#_ REGISTER_OUT v5 [03020100, 07060504, 0B0A0908, 0F0E0D0C]
#_ REGISTER_OUT v7 [00020100, 00040003, 00060005, 00080007]
test_multiple_lvx_swizzle_permute:
# Complex test: multiple loads, swizzles, and permutes
#_ MEMORY_IN 0x0000000010001000 [11, 11, 11, 11, 22, 22, 22, 22, 33, 33, 33, 33, 44, 44, 44, 44]
#_ MEMORY_IN 0x0000000010001010 [55, 55, 55, 55, 66, 66, 66, 66, 77, 77, 77, 77, 88, 88, 88, 88]
#_ REGISTER_IN r4 0x0000000010001000
#_ REGISTER_IN v10 [00010203, 14151617, 08090A0B, 1C1D1E1F] # mixed permute control
li r5, 0
lvx v3, r4, r5
li r5, 16
lvx v4, r4, r5
# vpermwi128 v5, v3, 0x1B (identity: 0,1,2,3)
.long 0x189B1E10
# vpermwi128 v6, v4, 0xE4 (reverse: 3,2,1,0)
.long 0x18E42350
vperm v7, v5, v6, v10
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 16
#_ REGISTER_OUT v3 [00011100, 11001100, 22002200, 22002200]
#_ REGISTER_OUT v4 [00055500, 55005500, 08000180, 00180001]
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v6 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v7 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v10 [00010203, 14151617, 08090A0B, 1C1D1E1F]

78
src/xenia/cpu/ppc/testing/instr_lvxl.s Normal file
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test_lvxl_1:
# Basic aligned load with LRU hint
#_ MEMORY_IN 0x0000000010001000 [01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
lvxl v3, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT v3 [00010200, 03000400, 05000600, 07000800]
test_lvxl_2:
# Test with base+offset addressing
#_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, AA, BB, CC, DD, EE, FF, 11, 22]
#_ MEMORY_IN 0x0000000010001010 [33, 44, 55, 66, 77, 88, 99, 00, 11, 22, 33, 44, 55, 66, 77, 88]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 16
lvxl v3, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 16
#_ REGISTER_OUT v3 [00034400, 55006600, 77008800, 99000000]
test_lvxl_3:
# Test unaligned address (should mask to 16-byte boundary)
#_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88, 99, AA, BB, CC, DD, EE, FF, 00]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 7 # unaligned offset
lvxl v3, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 7
# Should load from aligned address 0x10001000 (masks low 4 bits)
#_ REGISTER_OUT v3 [00012200, 33004400, 55006600, 77008800]
test_lvxl_4:
# Test with zero base register
#_ MEMORY_IN 0x0000000010001000 [FF, EE, DD, CC, BB, AA, 99, 88, 77, 66, 55, 44, 33, 22, 11, 00]
#_ REGISTER_IN r4 0
lis r5, 0x1000
addi r5, r5, 0x1000
lvxl v3, r4, r5
blr
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 0x10001000
#_ REGISTER_OUT v3 [000FEE00, DD00CC00, BB00AA00, 99008800]
test_lvxl_5:
# Test loading multiple vectors with LRU hints (cache behavior)
#_ MEMORY_IN 0x0000000010001000 [AA, AA, AA, AA, BB, BB, BB, BB, CC, CC, CC, CC, DD, DD, DD, DD]
#_ MEMORY_IN 0x0000000010001010 [11, 22, 33, 44, 55, 66, 77, 88, 99, AA, BB, CC, DD, EE, FF, 00]
#_ MEMORY_IN 0x0000000010001020 [F0, E1, D2, C3, B4, A5, 96, 87, 78, 69, 5A, 4B, 3C, 2D, 1E, 0F]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
lvxl v3, r4, r5
li r5, 16
lvxl v4, r4, r5
li r5, 32
lvxl v5, r4, r5
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 32
#_ REGISTER_OUT v3 [000AAA00, AA00AA00, BB00BB00, BB00BB00]
#_ REGISTER_OUT v4 [00012200, 33004400, 55006600, 77008800]
#_ REGISTER_OUT v5 [0000E100, D200C300, B400A500, 96008700]
test_lvxl_6:
# Verify lvxl behaves identically to lvx (LRU is just a cache hint)
#_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 9A, BC, DE, F0, FE, DC, BA, 98, 76, 54, 32, 10]
#_ REGISTER_IN r4 0x0000000010001000
li r5, 0
lvx v3, r4, r5 # First load with lvx
lvxl v4, r4, r5 # Second load with lvxl - should be identical
blr
#_ REGISTER_OUT r4 0x0000000010001000
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT v3 [00023400, 56007800, 9A00BC00, DE00F000]
#_ REGISTER_OUT v4 [00023400, 56007800, 9A00BC00, DE00F000]