Switching to premake. Probably with disasterous consequences.

src/xenia/cpu/frontend/testing/README.md

@@ -0,0 +1,61 @@
+# Codegen Tests
+
+This directory contains the test assets used by the automated codegen test
+runner.
+
+Each test is structured as a source `[name].s` PPC assembly file and the
+generated outputs. The outputs are made using the custom build of binutils
+setup when `xenia-build setup` is called and are checked in to make it easier
+to run the tests on Windows.
+
+Tests are run using the `xenia-test` app or via `xenia-build test`.
+
+## Execution
+
+The test binary is placed into memory at `0x82010000` and all other memory is
+zeroed.
+
+All registers are reset to zero. In order to provide useful inputs tests can
+specify `# REGISTER_IN` values.
+
+The code is jumped into at the starting address and executed until the last
+instruction in the input file is reached.
+
+After all instructions complete any `# REGISTER_OUT` values are checked and if
+they do not match the test is failed.
+
+## Annotations
+
+Annotations can appear at any line in a file. If a number is required it can
+be in either hex or decimal form, or IEEE if floating-point.
+
+### REGISTER_IN
+
+```
+# REGISTER_IN [register name] [register value]
+```
+
+Sets the value of a register prior to executing the instructions.
+
+Examples:
+```
+# REGISTER_IN r4 0x1234
+# REGISTER_IN r4 5678
+```
+
+### REGISTER_OUT
+
+```
+# REGISTER_OUT [register name] [register value]
+```
+
+Defines the expected register value when the instructions have executed.
+If after all instructions have completed the register value does not match
+the value given here the test will fail.
+
+Examples:
+```
+# REGISTER_OUT r3 123
+```
+
+TODO: memory setup/assertions

src/xenia/cpu/frontend/testing/instr_add.s

@@ -0,0 +1,178 @@
+test_add_1:
+  #_ REGISTER_IN r5 0x00100000
+  #_ REGISTER_IN r25 0x0000FFFF
+
+  add r11, r5, r25
+
+  blr
+  #_ REGISTER_OUT r5 0x00100000
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x0010FFFF
+
+test_add_1_constant:
+  lis r5, 0x10
+  li r25, -1
+  clrldi r25, r25, 48
+
+  add r11, r5, r25
+
+  blr
+  #_ REGISTER_OUT r5 0x00100000
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x0010FFFF
+
+test_add_2:
+  #_ REGISTER_IN r0 0x00100000
+  #_ REGISTER_IN r25 0x0000FFFF
+
+  add r11, r0, r25
+
+  blr
+  #_ REGISTER_OUT r0 0x00100000
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x0010FFFF
+
+test_add_2_constant:
+  lis r0, 0x10
+  li r25, -1
+  clrldi r25, r25, 48
+
+  add r11, r0, r25
+
+  blr
+  #_ REGISTER_OUT r0 0x00100000
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x0010FFFF
+
+test_add_cr_1:
+  #_ REGISTER_IN r5 0x00100000
+  #_ REGISTER_IN r25 0x0000FFFF
+
+  add. r11, r5, r25
+  mfcr r12
+
+  blr
+  #_ REGISTER_OUT r5 0x00100000
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x0010FFFF
+  #_ REGISTER_OUT r12 0x40000000
+
+test_add_cr_1_constant:
+  lis r5, 0x10
+  li r25, -1
+  clrldi r25, r25, 48
+
+  add. r11, r5, r25
+  mfcr r12
+
+  blr
+  #_ REGISTER_OUT r5 0x00100000
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x0010FFFF
+  #_ REGISTER_OUT r12 0x40000000
+
+test_add_cr_2:
+  #_ REGISTER_IN r0 0x00100000
+  #_ REGISTER_IN r25 0x0000FFFF
+
+  add. r11, r0, r25
+  mfcr r12
+
+  blr
+  #_ REGISTER_OUT r0 0x00100000
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x0010FFFF
+  #_ REGISTER_OUT r12 0x40000000
+
+test_add_cr_2_constant:
+  lis r0, 0x10
+  li r25, -1
+  clrldi r25, r25, 48
+
+  add. r11, r0, r25
+  mfcr r12
+
+  blr
+  #_ REGISTER_OUT r0 0x00100000
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x0010FFFF
+  #_ REGISTER_OUT r12 0x40000000
+
+test_add_cr_3:
+  #_ REGISTER_IN r0 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0x000000000000FFFF
+
+  add. r11, r0, r25
+  mfcr r12
+
+  blr
+  #_ REGISTER_OUT r0 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0x000000000000FFFF
+  #_ REGISTER_OUT r11 0x000000000000FFFE
+  #_ REGISTER_OUT r12 0x40000000
+
+test_add_cr_3_constant:
+  li r0, -1
+  li r25, -1
+  clrldi r25, r25, 48
+
+  add. r11, r0, r25
+  mfcr r12
+
+  blr
+  #_ REGISTER_OUT r0 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0x000000000000FFFF
+  #_ REGISTER_OUT r11 0x000000000000FFFE
+  #_ REGISTER_OUT r12 0x40000000
+
+test_add_cr_4:
+  #_ REGISTER_IN r0 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0x0000000000000001
+
+  add. r11, r0, r25
+  mfcr r12
+
+  blr
+  #_ REGISTER_OUT r0 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0x0000000000000001
+  #_ REGISTER_OUT r11 0x0000000000000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_add_cr_4_constant:
+  li r0, -1
+  li r25, 1
+
+  add. r11, r0, r25
+  mfcr r12
+
+  blr
+  #_ REGISTER_OUT r0 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0x0000000000000001
+  #_ REGISTER_OUT r11 0x0000000000000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_add_cr_5:
+  #_ REGISTER_IN r0 -50
+  #_ REGISTER_IN r25 -25
+
+  add. r11, r0, r25
+  mfcr r12
+
+  blr
+  #_ REGISTER_OUT r0 -50
+  #_ REGISTER_OUT r25 -25
+  #_ REGISTER_OUT r11 -75
+  #_ REGISTER_OUT r12 0x80000000
+
+test_add_cr_5_constant:
+  li r0, -50
+  li r25, -25
+
+  add. r11, r0, r25
+  mfcr r12
+
+  blr
+  #_ REGISTER_OUT r0 -50
+  #_ REGISTER_OUT r25 -25
+  #_ REGISTER_OUT r11 -75
+  #_ REGISTER_OUT r12 0x80000000

src/xenia/cpu/frontend/testing/instr_addc.s

@@ -0,0 +1,266 @@
+test_addc_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  addc r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 3
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+
+test_addc_1_constant:
+  li r4, 1
+  li r5, 2
+  addc r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 3
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+
+test_addc_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  addc r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+
+test_addc_2_constant:
+  li r4, -1
+  li r5, 0
+  addc r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+
+test_addc_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  addc r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+
+test_addc_3_constant:
+  li r4, -1
+  li r5, 1
+  addc r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+
+test_addc_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 123
+  addc r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007A
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+
+test_addc_4_constant:
+  li r4, -1
+  li r5, 123
+  addc r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007A
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+
+test_addc_5:
+  #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  addc r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_addc_5_constant:
+  li r5, -1
+  srdi r4, r5, 1
+  addc r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_addc_cr_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 3
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addc_cr_1_constant:
+  li r4, 1
+  li r5, 2
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 3
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addc_cr_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addc_cr_2_constant:
+  li r4, -1
+  li r5, 0
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addc_cr_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addc_cr_3_constant:
+  li r4, -1
+  li r5, 1
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addc_cr_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 123
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007A
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addc_cr_4_constant:
+  li r4, -1
+  li r5, 123
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007A
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addc_cr_5:
+  #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addc_cr_5_constant:
+  li r5, -1
+  srdi r4, r5, 1
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addc_cr_6:
+  #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 2
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000001
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addc_cr_6_constant:
+  li r4, -1
+  srdi r4, r4, 1
+  li r5, 2
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000001
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x40000000

src/xenia/cpu/frontend/testing/instr_adde.s

@@ -0,0 +1,579 @@
+test_adde_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 3
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+
+test_adde_1_constant:
+  li r4, 1
+  li r5, 2
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 3
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+
+test_adde_2:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 4
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+
+test_adde_2_constant:
+  li r4, 1
+  li r5, 2
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 4
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+
+test_adde_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+
+test_adde_3_constant:
+  li r4, -1
+  li r5, 0
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+
+test_adde_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 1
+
+test_adde_4_constant:
+  li r4, -1
+  li r5, 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 1
+
+test_adde_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+
+test_adde_5_constant:
+  li r4, -1
+  li r5, 1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+
+test_adde_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+
+test_adde_6_constant:
+  li r4, -1
+  li r5, 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+
+test_adde_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 123
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007A
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+
+test_adde_7_constant:
+  li r4, -1
+  li r5, 123
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007A
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+
+test_adde_8:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 123
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007B
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+
+test_adde_8_constant:
+  li r4, -1
+  li r5, 123
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007B
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+
+test_adde_9:
+  #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_adde_9_constant:
+  li r5, -1
+  srdi r4, r5, 1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_adde_10:
+  #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_adde_10_constant:
+  li r5, -1
+  srdi r4, r5, 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_adde_cr_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 3
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r11 0x40000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_adde_cr_1_constant:
+  li r4, 1
+  li r5, 2
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 3
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r11 0x40000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_adde_cr_2:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr 12
+  blr
+  #_ REGISTER_OUT r3 4
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r11 0x40000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_adde_cr_2_constant:
+  li r4, 1
+  li r5, 2
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 4
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r11 0x40000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_adde_cr_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r11 0x80000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_adde_cr_3_constant:
+  li r4, -1
+  li r5, 0
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r11 0x80000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_adde_cr_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x20000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_4_constant:
+  li r4, -1
+  li r5, 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x20000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x20000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_5_constant:
+  li r4, -1
+  li r5, 1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x20000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x40000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_6_constant:
+  li r4, -1
+  li r5, 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x40000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 123
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007A
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x40000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_7_constant:
+  li r4, -1
+  li r5, 123
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007A
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x40000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_8:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 123
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007B
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x40000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_8_constant:
+  li r4, -1
+  li r5, 123
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007B
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x40000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_9:
+  #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x80000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_9_constant:
+  li r5, -1
+  srdi r4, r5, 1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x80000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_10:
+  #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x80000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_adde_cr_10_constant:
+  li r5, -1
+  srdi r4, r5, 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  adde. r3, r4, r5
+  mfcr r11
+  adde. r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r11 0x80000000
+  #_ REGISTER_OUT r12 0x40000000

src/xenia/cpu/frontend/testing/instr_addic.s

@@ -0,0 +1,88 @@
+test_addic_1:
+  #_ REGISTER_IN r4 1
+  addic r4, r4, 1
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r6 0
+
+test_addic_1_constant:
+  li r4, 1
+  addic r4, r4, 1
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r6 0
+
+test_addic_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  addic r4, r4, 1
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 1
+
+test_addic_2_constant:
+  li r4, -1
+  addic r4, r4, 1
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 1
+
+test_addic_3:
+  #_ REGISTER_IN r4 0xFFFFFFFF
+  addic r4, r4, 1
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r4 0x0000000100000000
+  #_ REGISTER_OUT r6 1
+
+test_addic_3_constant:
+  li r4, 0xFFFFFFFF
+  srw r4, r4, 0
+  addic r4, r4, 1
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r4 0x0000000100000000
+  #_ REGISTER_OUT r6 1
+
+test_addic_cr_1:
+  #_ REGISTER_IN r4 1
+  addic. r4, r4, 1
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addic_cr_1_constant:
+  li r4, 1
+  addic. r4, r4, 1
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addic_cr_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  addic. r4, r4, 1
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addic_cr_2_constant:
+  li r4, -1
+  addic. r4, r4, 1
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000

src/xenia/cpu/frontend/testing/instr_addis.s

@@ -0,0 +1,77 @@
+test_addis_1:
+  #_ REGISTER_IN r0 1234
+  #_ REGISTER_IN r4 1
+  addis r3, r0, 1
+  blr
+  #_ REGISTER_OUT r0 1234
+  #_ REGISTER_OUT r3 0x10000
+  #_ REGISTER_OUT r4 1
+
+test_addis_1_constant:
+  li r0, 1234
+  li r4, 1
+  addis r3, r0, 1
+  blr
+  #_ REGISTER_OUT r0 1234
+  #_ REGISTER_OUT r3 0x10000
+  #_ REGISTER_OUT r4 1
+
+test_addis_2:
+  #_ REGISTER_IN r4 1234
+  #_ REGISTER_IN r5 1
+  addis r3, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0x104D2
+  #_ REGISTER_OUT r4 1234
+
+test_addis_2_constant:
+  li r4, 1234
+  li r5, 1
+  addis r3, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0x104D2
+  #_ REGISTER_OUT r4 1234
+
+test_lis_1:
+  #_ REGISTER_IN r0 1234
+  lis r3, 1
+  blr
+  #_ REGISTER_OUT r0 1234
+  #_ REGISTER_OUT r3 0x10000
+
+test_lis_1_constant:
+  li r0, 1234
+  lis r3, 1
+  blr
+  #_ REGISTER_OUT r0 1234
+  #_ REGISTER_OUT r3 0x10000
+
+test_lis_2:
+  #_ REGISTER_IN r0 1234
+  lis r3, -1
+  blr
+  #_ REGISTER_OUT r0 1234
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF0000
+
+test_lis_2_constant:
+  li r0, 1234
+  lis r3, -1
+  blr
+  #_ REGISTER_OUT r0 1234
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF0000
+
+test_subis_1:
+  #_ REGISTER_IN r4 1234
+  #_ REGISTER_IN r5 1
+  subis r3, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF04D2
+  #_ REGISTER_OUT r4 1234
+
+test_subis_1_constant:
+  li r4, 1234
+  li r5, 1
+  subis r3, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF04D2
+  #_ REGISTER_OUT r4 1234

src/xenia/cpu/frontend/testing/instr_addme.s

@@ -0,0 +1,367 @@
+test_addme_1:
+  #_ REGISTER_IN r4 1
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 1
+
+test_addme_1_constant:
+  li r4, 1
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 1
+
+test_addme_2:
+  #_ REGISTER_IN r4 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 1
+
+test_addme_2_constant:
+  li r4, 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 1
+
+test_addme_3:
+  #_ REGISTER_IN r4 12
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 11
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 1
+
+test_addme_3_constant:
+  li r4, 12
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 11
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 1
+
+test_addme_4:
+  #_ REGISTER_IN r4 12
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 12
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 1
+
+test_addme_4_constant:
+  li r4, 12
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 12
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 1
+
+test_addme_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_addme_5_constant:
+  li r4, -1
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_addme_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_addme_6_constant:
+  li r4, -1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_addme_7:
+  #_ REGISTER_IN r4 0
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 0
+
+test_addme_7_constant:
+  li r4, 0
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 0
+
+test_addme_8:
+  #_ REGISTER_IN r4 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 1
+
+test_addme_8_constant:
+  li r4, 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 1
+
+test_addme_cr_1:
+  #_ REGISTER_IN r4 1
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addme_cr_1_constant:
+  li r4, 1
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addme_cr_2:
+  #_ REGISTER_IN r4 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addme_cr_2_constant:
+  li r4, 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addme_cr_3:
+  #_ REGISTER_IN r4 12
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 11
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addme_cr_3_constant:
+  li r4, 12
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 11
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addme_cr_4:
+  #_ REGISTER_IN r4 12
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 12
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addme_cr_4_constant:
+  li r4, 12
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 12
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addme_cr_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addme_cr_5_constant:
+  li r4, -1
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addme_cr_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addme_cr_6_constant:
+  li r4, -1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addme_cr_7:
+  #_ REGISTER_IN r4 0
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addme_cr_7_constant:
+  li r4, 0
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addme_cr_8:
+  #_ REGISTER_IN r4 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addme_cr_8_constant:
+  li r4, 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addme. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000

src/xenia/cpu/frontend/testing/instr_addze.s

@@ -0,0 +1,367 @@
+test_addze_1:
+  #_ REGISTER_IN r4 1
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 0
+
+test_addze_1_constant:
+  li r4, 1
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 0
+
+test_addze_2:
+  #_ REGISTER_IN r4 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 0
+
+test_addze_2_constant:
+  li r4, 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 0
+
+test_addze_3:
+  #_ REGISTER_IN r4 12
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 12
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 0
+
+test_addze_3_constant:
+  li r4, 12
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 12
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 0
+
+test_addze_4:
+  #_ REGISTER_IN r4 12
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 13
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 0
+
+test_addze_4_constant:
+  li r4, 12
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 13
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 0
+
+test_addze_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 0
+
+test_addze_5_constant:
+  li r4, -1
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 0
+
+test_addze_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_addze_6_constant:
+  li r4, -1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_addze_7:
+  #_ REGISTER_IN r4 0
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 0
+
+test_addze_7_constant:
+  li r4, 0
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 0
+
+test_addze_8:
+  #_ REGISTER_IN r4 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 0
+
+test_addze_8_constant:
+  li r4, 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze r3, r4
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 0
+
+test_addze_cr_1:
+  #_ REGISTER_IN r4 1
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addze_cr_1_constant:
+  li r4, 1
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addze_cr_2:
+  #_ REGISTER_IN r4 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addze_cr_2_constant:
+  li r4, 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addze_cr_3:
+  #_ REGISTER_IN r4 12
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 12
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addze_cr_3_constant:
+  li r4, 12
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 12
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addze_cr_4:
+  #_ REGISTER_IN r4 12
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 13
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addze_cr_4_constant:
+  li r4, 12
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 13
+  #_ REGISTER_OUT r4 12
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addze_cr_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addze_cr_5_constant:
+  li r4, -1
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addze_cr_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addze_cr_6_constant:
+  li r4, -1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addze_cr_7:
+  #_ REGISTER_IN r4 0
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addze_cr_7_constant:
+  li r4, 0
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addze_cr_8:
+  #_ REGISTER_IN r4 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addze_cr_8_constant:
+  li r4, 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1 # CA=1
+  addze. r3, r4
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000

src/xenia/cpu/frontend/testing/instr_and.s

@@ -0,0 +1,205 @@
+test_and_1:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
+  and r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+
+test_and_1_constant:
+  li r5, -1
+  li r25, -1
+  and r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+
+test_and_2:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0
+  and r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0
+  #_ REGISTER_OUT r11 0
+
+test_and_2_constant:
+  li r5, -1
+  li r25, 0
+  and r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0
+  #_ REGISTER_OUT r11 0
+
+test_and_3:
+  #_ REGISTER_IN r5 0
+  #_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
+  and r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0
+
+test_and_3_constant:
+  li r5, 0
+  li r25, -1
+  and r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0
+
+test_and_4:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0x0000FFFF
+  and r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x0000FFFF
+
+test_and_4_constant:
+  li r5, -1
+  li r25, -1
+  clrldi r25, r25, 48
+  and r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x0000FFFF
+
+test_and_5:
+  #_ REGISTER_IN r0 0x100000FF
+  #_ REGISTER_IN r25 0x0000FFFF
+  and r11, r0, r25
+  blr
+  #_ REGISTER_OUT r0 0x100000FF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x000000FF
+
+test_and_5_constant:
+  lis r0, 0x1000
+  ori r0, r0, 0xFF
+  li r25, -1
+  clrldi r25, r25, 48
+  and r11, r0, r25
+  blr
+  #_ REGISTER_OUT r0 0x100000FF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x000000FF
+
+test_and_cr_1:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
+  and. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r12 0x80000000
+
+test_and_cr_1_constant:
+  li r5, -1
+  li r25, -1
+  and. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r12 0x80000000
+
+test_and_cr_2:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0
+  and. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_and_cr_2_constant:
+  li r5, -1
+  li r25, 0
+  and. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_and_cr_3:
+  #_ REGISTER_IN r5 0
+  #_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
+  and. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_and_cr_3_constant:
+  li r5, 0
+  li r25, -1
+  and. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_and_cr_4:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0x0000FFFF
+  and. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x0000FFFF
+  #_ REGISTER_OUT r12 0x40000000
+
+test_and_cr_4_constant:
+  li r5, -1
+  li r25, -1
+  clrldi r25, r25, 48
+  and. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x0000FFFF
+  #_ REGISTER_OUT r12 0x40000000
+
+test_and_cr_5:
+  #_ REGISTER_IN r0 0x100000FF
+  #_ REGISTER_IN r25 0x0000FFFF
+  and. r11, r0, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r0 0x100000FF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x000000FF
+  #_ REGISTER_OUT r12 0x40000000
+
+test_and_cr_5_constant:
+  lis r0, 0x1000
+  ori r0, r0, 0xFF
+  li r25, -1
+  clrldi r25, r25, 48
+  and. r11, r0, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r0 0x100000FF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x000000FF
+  #_ REGISTER_OUT r12 0x40000000

src/xenia/cpu/frontend/testing/instr_andc.s

@@ -0,0 +1,205 @@
+test_andc_1:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
+  andc r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0
+
+test_andc_1_constant:
+  li r5, -1
+  li r25, -1
+  andc r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0
+
+test_andc_2:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0
+  andc r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+
+test_andc_2_constant:
+  li r5, -1
+  li r25, 0
+  andc r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+
+test_andc_3:
+  #_ REGISTER_IN r5 0
+  #_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
+  andc r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0
+
+test_andc_3_constant:
+  li r5, 0
+  li r25, -1
+  andc r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0
+
+test_andc_4:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0x0000FFFF
+  andc r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFF0000
+
+test_andc_4_constant:
+  li r5, -1
+  li r25, -1
+  clrldi r25, r25, 48
+  andc r11, r5, r25
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFF0000
+
+test_andc_5:
+  #_ REGISTER_IN r0 0x100000FF
+  #_ REGISTER_IN r25 0x0000FFFF
+  andc r11, r0, r25
+  blr
+  #_ REGISTER_OUT r0 0x100000FF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x10000000
+
+test_andc_5_constant:
+  lis r0, 0x1000
+  ori r0, r0, 0xFF
+  li r25, -1
+  clrldi r25, r25, 48
+  andc r11, r0, r25
+  blr
+  #_ REGISTER_OUT r0 0x100000FF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x10000000
+
+test_andc_cr_1:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
+  andc. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_andc_cr_1_constant:
+  li r5, -1
+  li r25, -1
+  andc. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_andc_cr_2:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0
+  andc. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r12 0x80000000
+
+test_andc_cr_2_constant:
+  li r5, -1
+  li r25, 0
+  andc. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r12 0x80000000
+
+test_andc_cr_3:
+  #_ REGISTER_IN r5 0
+  #_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
+  andc. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_andc_cr_3_constant:
+  li r5, 0
+  li r25, -1
+  andc. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_andc_cr_4:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r25 0x0000FFFF
+  andc. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFF0000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_andc_cr_4_constant:
+  li r5, -1
+  li r25, -1
+  clrldi r25, r25, 48
+  andc. r11, r5, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFF0000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_andc_cr_5:
+  #_ REGISTER_IN r0 0x100000FF
+  #_ REGISTER_IN r25 0x0000FFFF
+  andc. r11, r0, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r0 0x100000FF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x10000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_andc_cr_5_constant:
+  lis r0, 0x1000
+  ori r0, r0, 0xFF
+  li r25, -1
+  clrldi r25, r25, 48
+  andc. r11, r0, r25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r0 0x100000FF
+  #_ REGISTER_OUT r25 0x0000FFFF
+  #_ REGISTER_OUT r11 0x10000000
+  #_ REGISTER_OUT r12 0x40000000

src/xenia/cpu/frontend/testing/instr_andi.s

@@ -0,0 +1,90 @@
+test_andi_cr_1:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  andi. r11, r5, 0xCAFE
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0x0000CAFE
+  #_ REGISTER_OUT r12 0x40000000
+
+test_andi_cr_1_constant:
+  li r5, -1
+  andi. r11, r5, 0xCAFE
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0x0000CAFE
+  #_ REGISTER_OUT r12 0x40000000
+
+test_andi_cr_2:
+ #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+ andi. r11, r5, 0
+ mfcr r12
+ blr
+ #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+ #_ REGISTER_OUT r11 0
+ #_ REGISTER_OUT r12 0x20000000
+
+test_andi_cr_2_constant:
+ #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+ andi. r11, r5, 0
+ mfcr r12
+ blr
+ #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+ #_ REGISTER_OUT r11 0
+ #_ REGISTER_OUT r12 0x20000000
+
+test_andi_cr_3:
+  #_ REGISTER_IN r5 0
+  andi. r11, r5, 0xFFFF
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_andi_cr_3_constant:
+  li r5, 0
+  andi. r11, r5, 0xFFFF
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_andi_cr_4:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  andi. r11, r5, 0xCAFE
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0x0000CAFE
+  #_ REGISTER_OUT r12 0x40000000
+
+test_andi_cr_4_constant:
+  li r5, -1
+  andi. r11, r5, 0xCAFE
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0x0000CAFE
+  #_ REGISTER_OUT r12 0x40000000
+
+test_andi_cr_5:
+  #_ REGISTER_IN r0 0x100000FF
+  andi. r11, r0, 0xFFFF
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r0 0x100000FF
+  #_ REGISTER_OUT r11 0x000000FF
+  #_ REGISTER_OUT r12 0x40000000
+
+test_andi_cr_5_constant:
+  lis r0, 0x1000
+  ori r0, r0, 0xFF
+  andi. r11, r0, 0xFFFF
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r0 0x100000FF
+  #_ REGISTER_OUT r11 0x000000FF
+  #_ REGISTER_OUT r12 0x40000000

src/xenia/cpu/frontend/testing/instr_andis.s

@@ -0,0 +1,90 @@
+test_andis_cr_1:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  andis. r11, r5, 0xCAFE
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xCAFE0000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_andis_cr_1_constant:
+  li r5, -1
+  andis. r11, r5, 0xCAFE
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xCAFE0000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_andis_cr_2:
+ #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+ andis. r11, r5, 0
+ mfcr r12
+ blr
+ #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+ #_ REGISTER_OUT r11 0
+ #_ REGISTER_OUT r12 0x20000000
+
+test_andis_cr_2_constant:
+ #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+ andis. r11, r5, 0
+ mfcr r12
+ blr
+ #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+ #_ REGISTER_OUT r11 0
+ #_ REGISTER_OUT r12 0x20000000
+
+test_andis_cr_3:
+  #_ REGISTER_IN r5 0
+  andis. r11, r5, 0xFFFF
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_andis_cr_3_constant:
+  li r5, 0
+  andis. r11, r5, 0xFFFF
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r12 0x20000000
+
+test_andis_cr_4:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  andis. r11, r5, 0xCAFE
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xCAFE0000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_andis_cr_4_constant:
+  li r5, -1
+  andis. r11, r5, 0xCAFE
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xCAFE0000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_andis_cr_5:
+  #_ REGISTER_IN r0 0x100000FF
+  andis. r11, r0, 0xFFFF
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r0 0x100000FF
+  #_ REGISTER_OUT r11 0x10000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_andis_cr_5_constant:
+  lis r0, 0x1000
+  ori r0, r0, 0xFF
+  andis. r11, r0, 0xFFFF
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r0 0x100000FF
+  #_ REGISTER_OUT r11 0x10000000
+  #_ REGISTER_OUT r12 0x40000000

src/xenia/cpu/frontend/testing/instr_cmp.s

@@ -0,0 +1,186 @@
+test_cmpd_1:
+  #_ REGISTER_IN r3 0x0000000100000000
+  #_ REGISTER_IN r4 0x0000000200000000
+  cmpd r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r4 0x0000000200000000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmpd_1_constant:
+  li r3, 1
+  sldi r3, r3, 32
+  sldi r4, r3, 1
+  cmpd r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r4 0x0000000200000000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmpd_2:
+  #_ REGISTER_IN r3 0x0000000200000000
+  #_ REGISTER_IN r4 0x0000000100000000
+  cmpd r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000200000000
+  #_ REGISTER_OUT r4 0x0000000100000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpd_2_constant:
+  li r4, 1
+  sldi r4, r4, 32
+  sldi r3, r4, 1
+  cmpd r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000200000000
+  #_ REGISTER_OUT r4 0x0000000100000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpw_1:
+  #_ REGISTER_IN r3 0x0000000100000000
+  #_ REGISTER_IN r4 0x0000000200000000
+  cmpw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r4 0x0000000200000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_cmpw_1_constant:
+  li r3, 1
+  sldi r3, r3, 32
+  sldi r4, r3, 1
+  cmpw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r4 0x0000000200000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_cmpw_2:
+  #_ REGISTER_IN r3 0x0000000200000000
+  #_ REGISTER_IN r4 0x0000000100000000
+  cmpw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000200000000
+  #_ REGISTER_OUT r4 0x0000000100000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_cmpw_2_constant:
+  li r4, 1
+  sldi r4, r4, 32
+  sldi r3, r4, 1
+  cmpw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000200000000
+  #_ REGISTER_OUT r4 0x0000000100000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_cmpw_3:
+  #_ REGISTER_IN r3 1
+  #_ REGISTER_IN r4 2
+  cmpw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmpw_3_constant:
+  li r3, 1
+  li r4, 2
+  cmpw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmpw_4:
+  #_ REGISTER_IN r3 2
+  #_ REGISTER_IN r4 1
+  cmpw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpw_4_constant:
+  li r3, 2
+  li r4, 1
+  cmpw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpw_5:
+  #_ REGISTER_IN r3 0x0000000100000002
+  #_ REGISTER_IN r4 0x0000000200000001
+  cmpw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000002
+  #_ REGISTER_OUT r4 0x0000000200000001
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpw_5_constant:
+  li r3, 1
+  sldi r3, r3, 32
+  sldi r4, r3, 1
+  addi r3, r3, 2
+  addi r4, r4, 1
+  cmpw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000002
+  #_ REGISTER_OUT r4 0x0000000200000001
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmp_1:
+  #_ REGISTER_IN r3 1
+  #_ REGISTER_IN r4 2
+  cmp 5, 0, r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r12 0x00000800
+
+test_cmp_1_constant:
+  li r3, 1
+  li r4, 2
+  cmp 5, 0, r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r12 0x00000800
+
+test_cmp_2:
+  #_ REGISTER_IN r3 2
+  #_ REGISTER_IN r4 1
+  cmp 3, 0, r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r12 0x00040000
+
+test_cmp_2_constant:
+  li r3, 2
+  li r4, 1
+  cmp 3, 0, r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r12 0x00040000

src/xenia/cpu/frontend/testing/instr_cmpi.s

@@ -0,0 +1,116 @@
+test_cmpdi_1:
+  #_ REGISTER_IN r3 0x0000000100000000
+  cmpdi r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpdi_1_constant:
+  li r3, 1
+  sldi r3, r3, 32
+  cmpdi r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpdi_2:
+  #_ REGISTER_IN r3 1
+  cmpdi r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmpdi_2_constant:
+  li r3, 1
+  cmpdi r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmpwi_1:
+  #_ REGISTER_IN r3 0x0000000100000000
+  cmpwi r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmpwi_1_constant:
+  li r3, 1
+  sldi r3, r3, 32
+  cmpwi r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmpwi_2:
+  #_ REGISTER_IN r3 2
+  cmpwi r3, 1
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpwi_2_constant:
+  li r3, 2
+  cmpwi r3, 1
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpwi_5:
+  #_ REGISTER_IN r3 0x0000000100000002
+  cmpwi r3, 1
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000002
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpwi_5_constant:
+  li r3, 1
+  sldi r3, r3, 32
+  sldi r4, r3, 1
+  addi r3, r3, 2
+  cmpwi r3, 1
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000002
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpi_1:
+  #_ REGISTER_IN r3 1
+  cmpi 5, 0, r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r12 0x00000800
+
+test_cmpi_1_constant:
+  li r3, 1
+  cmpi 5, 0, r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r12 0x00000800
+
+test_cmpi_2:
+  #_ REGISTER_IN r3 2
+  cmpi 3, 0, r3, 1
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r12 0x00040000
+
+test_cmpi_2_constant:
+  li r3, 2
+  cmpi 3, 0, r3, 1
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r12 0x00040000

src/xenia/cpu/frontend/testing/instr_cmpl.s

@@ -0,0 +1,209 @@
+test_cmpld_1:
+  #_ REGISTER_IN r3 0x0000000100000000
+  #_ REGISTER_IN r4 0x0000000200000000
+  cmpld r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r4 0x0000000200000000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmpld_1_constant:
+  li r3, 1
+  sldi r3, r3, 32
+  sldi r4, r3, 1
+  cmpld r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r4 0x0000000200000000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmpld_2:
+  #_ REGISTER_IN r3 0x0000000200000000
+  #_ REGISTER_IN r4 0x0000000100000000
+  cmpld r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000200000000
+  #_ REGISTER_OUT r4 0x0000000100000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpld_2_constant:
+  li r4, 1
+  sldi r4, r4, 32
+  sldi r3, r4, 1
+  cmpld r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000200000000
+  #_ REGISTER_OUT r4 0x0000000100000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmplw_1:
+  #_ REGISTER_IN r3 0x0000000100000000
+  #_ REGISTER_IN r4 0x0000000200000000
+  cmplw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r4 0x0000000200000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_cmplw_1_constant:
+  li r3, 1
+  sldi r3, r3, 32
+  sldi r4, r3, 1
+  cmplw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r4 0x0000000200000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_cmplw_2:
+  #_ REGISTER_IN r3 0x0000000200000000
+  #_ REGISTER_IN r4 0x0000000100000000
+  cmplw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000200000000
+  #_ REGISTER_OUT r4 0x0000000100000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_cmplw_2_constant:
+  li r4, 1
+  sldi r4, r4, 32
+  sldi r3, r4, 1
+  cmplw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000200000000
+  #_ REGISTER_OUT r4 0x0000000100000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_cmplw_3:
+  #_ REGISTER_IN r3 1
+  #_ REGISTER_IN r4 2
+  cmplw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmplw_3_constant:
+  li r3, 1
+  li r4, 2
+  cmplw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmplw_4:
+  #_ REGISTER_IN r3 2
+  #_ REGISTER_IN r4 1
+  cmplw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmplw_4_constant:
+  li r3, 2
+  li r4, 1
+  cmplw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmplw_5:
+  #_ REGISTER_IN r3 0x0000000100000002
+  #_ REGISTER_IN r4 0x0000000200000001
+  cmplw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000002
+  #_ REGISTER_OUT r4 0x0000000200000001
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmplw_5_constant:
+  li r3, 1
+  sldi r3, r3, 32
+  sldi r4, r3, 1
+  addi r3, r3, 2
+  addi r4, r4, 1
+  cmplw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000002
+  #_ REGISTER_OUT r4 0x0000000200000001
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmplw_6:
+  #_ REGISTER_IN r3 0xFFFFFFFF80000000
+  #_ REGISTER_IN r4 0x0000000080000000
+  cmplw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+  #_ REGISTER_OUT r4 0x0000000080000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_cmplw_6_constant:
+  lis r3, 0x7FFF
+  ori r3, r3, 0xFFFF
+  not r3, r3
+  li r4, 1
+  sldi r4, r4, 31
+  cmplw r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+  #_ REGISTER_OUT r4 0x0000000080000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_cmpl_1:
+  #_ REGISTER_IN r3 1
+  #_ REGISTER_IN r4 2
+  cmpl 5, 0, r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r12 0x00000800
+
+test_cmpl_1_constant:
+  li r3, 1
+  li r4, 2
+  cmpl 5, 0, r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r12 0x00000800
+
+test_cmpl_2:
+  #_ REGISTER_IN r3 2
+  #_ REGISTER_IN r4 1
+  cmpl 3, 0, r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r12 0x00040000
+
+test_cmpl_2_constant:
+  li r3, 2
+  li r4, 1
+  cmpl 3, 0, r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r12 0x00040000

src/xenia/cpu/frontend/testing/instr_cmpli.s

@@ -0,0 +1,116 @@
+test_cmpldi_1:
+  #_ REGISTER_IN r3 0x0000000100000000
+  cmpldi r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpldi_1_constant:
+  li r3, 1
+  sldi r3, r3, 32
+  cmpldi r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpldi_2:
+  #_ REGISTER_IN r3 1
+  cmpldi r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmpldi_2_constant:
+  li r3, 1
+  cmpldi r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmplwi_1:
+  #_ REGISTER_IN r3 0x0000000100000000
+  cmplwi r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmplwi_1_constant:
+  li r3, 1
+  sldi r3, r3, 32
+  cmplwi r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_cmplwi_2:
+  #_ REGISTER_IN r3 2
+  cmplwi r3, 1
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmplwi_2_constant:
+  li r3, 2
+  cmplwi r3, 1
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmplwi_5:
+  #_ REGISTER_IN r3 0x0000000100000002
+  cmplwi r3, 1
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000002
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmplwi_5_constant:
+  li r3, 1
+  sldi r3, r3, 32
+  sldi r4, r3, 1
+  addi r3, r3, 2
+  cmplwi r3, 1
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000100000002
+  #_ REGISTER_OUT r12 0x40000000
+
+test_cmpli_1:
+  #_ REGISTER_IN r3 1
+  cmpli 5, 0, r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r12 0x00000800
+
+test_cmpli_1_constant:
+  li r3, 1
+  cmpli 5, 0, r3, 2
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r12 0x00000800
+
+test_cmpli_2:
+  #_ REGISTER_IN r3 2
+  cmpli 3, 0, r3, 1
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r12 0x00040000
+
+test_cmpli_2_constant:
+  li r3, 2
+  cmpli 3, 0, r3, 1
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r12 0x00040000

src/xenia/cpu/frontend/testing/instr_cntlzd.s

@@ -0,0 +1,56 @@
+test_cntlzd_1:
+  #_ REGISTER_IN r5 0
+  cntlzd r6, r5
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 64
+
+test_cntlzd_1_constant:
+  li r5, 0
+  cntlzd r6, r5
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 64
+
+test_cntlzd_2:
+  #_ REGISTER_IN r5 1
+  cntlzd r6, r5
+  blr
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 63
+
+test_cntlzd_2_constant:
+  li r5, 1
+  cntlzd r6, r5
+  blr
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 63
+
+test_cntlzd_3:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  cntlzd r6, r5
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 0
+
+test_cntlzd_3_constant:
+  li r5, -1
+  cntlzd r6, r5
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 0
+
+test_cntlzd_4:
+  #_ REGISTER_IN r5 0x7FFFFFFFFFFFFFFF
+  cntlzd r6, r5
+  blr
+  #_ REGISTER_OUT r5 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_cntlzd_4_constant:
+  li r5, -1
+  srdi r5, r5, 1
+  cntlzd r6, r5
+  blr
+  #_ REGISTER_OUT r5 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1

src/xenia/cpu/frontend/testing/instr_cntlzw.s

@@ -0,0 +1,73 @@
+test_cntlzw_1:
+  #_ REGISTER_IN r5 0
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 32
+
+test_cntlzw_1_constant:
+  li r5, 0
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 32
+
+test_cntlzw_2:
+  #_ REGISTER_IN r5 1
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 31
+
+test_cntlzw_2_constant:
+  li r5, 1
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 31
+
+test_cntlzw_3:
+  #_ REGISTER_IN r5 0xFFFFFFFF
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF
+  #_ REGISTER_OUT r6 0
+
+test_cntlzw_3_constant:
+  li r5, -1
+  srwi r5, r5, 0
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF
+  #_ REGISTER_OUT r6 0
+
+test_cntlzw_4:
+  #_ REGISTER_IN r5 0x7FFFFFFF
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 0x7FFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_cntlzw_4_constant:
+  li r5, -1
+  srwi r5, r5, 1
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 0x7FFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_cntlzw_5:
+  #_ REGISTER_IN r5 0xFFFFFFFF00000001
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF00000001
+  #_ REGISTER_OUT r6 31
+
+test_cntlzw_5_constant:
+  li r5, -1
+  sldi r5, r5, 32
+  addi r5, r5, 1
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF00000001
+  #_ REGISTER_OUT r6 31

src/xenia/cpu/frontend/testing/instr_divd.s

@@ -0,0 +1,166 @@
+test_divd_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+
+test_divd_1_constant:
+  li r4, 1
+  li r5, 2
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+
+# TODO(benvanik): x64 ignore divide by zero (=0)
+#test_divd_2:
+#  #_ REGISTER_IN r4 1
+#  #_ REGISTER_IN r5 0
+#  divd r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 1
+#  #_ REGISTER_OUT r5 0
+
+# TODO(benvanik): x64 ignore divide by zero (=0)
+#test_divd_2_constant:
+#  li r4, 1
+#  li r5, 0
+#  divd r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 1
+#  #_ REGISTER_OUT r5 0
+
+test_divd_3:
+  #_ REGISTER_IN r4 2
+  #_ REGISTER_IN r5 1
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r5 1
+
+test_divd_3_constant:
+  li r4, 2
+  li r5, 1
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r5 1
+
+test_divd_4:
+  #_ REGISTER_IN r4 35
+  #_ REGISTER_IN r5 7
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 5
+  #_ REGISTER_OUT r4 35
+  #_ REGISTER_OUT r5 7
+
+test_divd_4_constant:
+  li r4, 35
+  li r5, 7
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 5
+  #_ REGISTER_OUT r4 35
+  #_ REGISTER_OUT r5 7
+
+test_divd_5:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 1
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_divd_5_constant:
+  li r4, 0
+  li r5, 1
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_divd_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divd_6_constant:
+  li r4, -1
+  li r5, 1
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divd_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divd_7_constant:
+  li r4, -1
+  li r5, -1
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divd_8:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divd_8_constant:
+  li r4, 1
+  li r5, -1
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+# TODO(benvanik): integer overflow (=0)
+#test_divd_9:
+#  #_ REGISTER_IN r4 0x8000000000000000
+#  #_ REGISTER_IN r5 -1
+#  divd r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 0x8000000000000000
+#  #_ REGISTER_OUT r5 -1
+
+# TODO(benvanik): integer overflow (=0)
+#test_divd_9_constant:
+#  li r4, 1
+#  sldi r4, r4, 63
+#  li r5, -1
+#  divd r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 0x8000000000000000
+#  #_ REGISTER_OUT r5 -1

src/xenia/cpu/frontend/testing/instr_divdu.s

@@ -0,0 +1,165 @@
+test_divdu_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+
+test_divdu_1_constant:
+  li r4, 1
+  li r5, 2
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+
+# TODO(benvanik): x64 ignore divide by zero (=0)
+#test_divdu_2:
+#  #_ REGISTER_IN r4 1
+#  #_ REGISTER_IN r5 0
+#  divdu r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 1
+#  #_ REGISTER_OUT r5 0
+
+# TODO(benvanik): x64 ignore divide by zero (=0)
+#test_divdu_2_constant:
+#  li r4, 1
+#  li r5, 0
+#  divdu r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 1
+#  #_ REGISTER_OUT r5 0
+
+test_divdu_3:
+  #_ REGISTER_IN r4 2
+  #_ REGISTER_IN r5 1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r5 1
+
+test_divdu_3_constant:
+  li r4, 2
+  li r5, 1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r5 1
+
+test_divdu_4:
+  #_ REGISTER_IN r4 35
+  #_ REGISTER_IN r5 7
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 5
+  #_ REGISTER_OUT r4 35
+  #_ REGISTER_OUT r5 7
+
+test_divdu_4_constant:
+  li r4, 35
+  li r5, 7
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 5
+  #_ REGISTER_OUT r4 35
+  #_ REGISTER_OUT r5 7
+
+test_divdu_5:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_divdu_5_constant:
+  li r4, 0
+  li r5, 1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_divdu_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divdu_6_constant:
+  li r4, -1
+  li r5, 1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divdu_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divdu_7_constant:
+  li r4, -1
+  li r5, -1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divdu_8:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divdu_8_constant:
+  li r4, 1
+  li r5, -1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divdu_9:
+  #_ REGISTER_IN r4 0x8000000000000000
+  #_ REGISTER_IN r5 -1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x8000000000000000
+  #_ REGISTER_OUT r5 -1
+
+# TODO(benvanik): integer overflow (=0)
+test_divdu_9_constant:
+  li r4, 1
+  sldi r4, r4, 63
+  li r5, -1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x8000000000000000
+  #_ REGISTER_OUT r5 -1

src/xenia/cpu/frontend/testing/instr_divw.s

@@ -0,0 +1,223 @@
+test_divw_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+
+test_divw_1_constant:
+  li r4, 1
+  li r5, 2
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+
+# TODO(benvanik): x64 ignore divide by zero (=0)
+#test_divw_2:
+#  #_ REGISTER_IN r4 1
+#  #_ REGISTER_IN r5 0
+#  divw r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 1
+#  #_ REGISTER_OUT r5 0
+
+# TODO(benvanik): x64 ignore divide by zero (=0)
+#test_divw_2_constant:
+#  li r4, 1
+#  li r5, 0
+#  divw r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 1
+#  #_ REGISTER_OUT r5 0
+
+test_divw_3:
+  #_ REGISTER_IN r4 2
+  #_ REGISTER_IN r5 1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r5 1
+
+test_divw_3_constant:
+  li r4, 2
+  li r5, 1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r5 1
+
+test_divw_4:
+  #_ REGISTER_IN r4 35
+  #_ REGISTER_IN r5 7
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 5
+  #_ REGISTER_OUT r4 35
+  #_ REGISTER_OUT r5 7
+
+test_divw_4_constant:
+  li r4, 35
+  li r5, 7
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 5
+  #_ REGISTER_OUT r4 35
+  #_ REGISTER_OUT r5 7
+
+test_divw_5:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_divw_5_constant:
+  li r4, 0
+  li r5, 1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_divw_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divw_6_constant:
+  li r4, -1
+  li r5, 1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divw_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divw_7_constant:
+  li r4, -1
+  li r5, -1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divw_8:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divw_8_constant:
+  li r4, 1
+  li r5, -1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divw_9:
+  #_ REGISTER_IN r4 0x000000007FFFFFFF
+  #_ REGISTER_IN r5 1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divw_9_constant:
+  li r4, -1
+  clrldi r4, r4, 33
+  li r5, 1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divw_10:
+  #_ REGISTER_IN r4 0x000000007FFFFFFF
+  #_ REGISTER_IN r5 0x000000007FFFFFFF
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+test_divw_10_constant:
+  li r4, -1
+  clrldi r4, r4, 33
+  mr r5, r4
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+test_divw_11:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0x000000007FFFFFFF
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+test_divw_11_constant:
+  li r4, 1
+  li r5, -1
+  clrldi r5, r5, 33
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+# TODO(benvanik): integer overflow (=0)
+#test_divw_12:
+#  #_ REGISTER_IN r4 0x80000000
+#  #_ REGISTER_IN r5 -1
+#  divw r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 0x80000000
+#  #_ REGISTER_OUT r5 -1
+
+# TODO(benvanik): integer overflow (=0)
+#test_divw_12_constant:
+#  li r4, 1
+#  srdi r4, 31
+#  li r5, -1
+#  divw r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 0x80000000
+#  #_ REGISTER_OUT r5 -1

src/xenia/cpu/frontend/testing/instr_divwu.s

@@ -0,0 +1,221 @@
+test_divwu_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+
+test_divwu_1_constant:
+  li r4, 1
+  li r5, 2
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+
+# TODO(benvanik): x64 ignore divide by zero (=0)
+#test_divwu_2:
+#  #_ REGISTER_IN r4 1
+#  #_ REGISTER_IN r5 0
+#  divwu r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 1
+#  #_ REGISTER_OUT r5 0
+
+# TODO(benvanik): x64 ignore divide by zero (=0)
+#test_divwu_2_constant:
+#  li r4, 1
+#  li r5, 0
+#  divwu r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 1
+#  #_ REGISTER_OUT r5 0
+
+test_divwu_3:
+  #_ REGISTER_IN r4 2
+  #_ REGISTER_IN r5 1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r5 1
+
+test_divwu_3_constant:
+  li r4, 2
+  li r5, 1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r5 1
+
+test_divwu_4:
+  #_ REGISTER_IN r4 35
+  #_ REGISTER_IN r5 7
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 5
+  #_ REGISTER_OUT r4 35
+  #_ REGISTER_OUT r5 7
+
+test_divwu_4_constant:
+  li r4, 35
+  li r5, 7
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 5
+  #_ REGISTER_OUT r4 35
+  #_ REGISTER_OUT r5 7
+
+test_divwu_5:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_divwu_5_constant:
+  li r4, 0
+  li r5, 1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_divwu_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divwu_6_constant:
+  li r4, -1
+  li r5, 1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divwu_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divwu_7_constant:
+  li r4, -1
+  li r5, -1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divwu_8:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divwu_8_constant:
+  li r4, 1
+  li r5, -1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divwu_9:
+  #_ REGISTER_IN r4 0x000000007FFFFFFF
+  #_ REGISTER_IN r5 1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divwu_9_constant:
+  li r4, -1
+  clrldi r4, r4, 33
+  li r5, 1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divwu_10:
+  #_ REGISTER_IN r4 0x000000007FFFFFFF
+  #_ REGISTER_IN r5 0x000000007FFFFFFF
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+test_divwu_10_constant:
+  li r4, -1
+  clrldi r4, r4, 33
+  mr r5, r4
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+test_divwu_11:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0x000000007FFFFFFF
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+test_divwu_11_constant:
+  li r4, 1
+  li r5, -1
+  clrldi r5, r5, 33
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+test_divwu_12:
+  #_ REGISTER_IN r4 0x80000000
+  #_ REGISTER_IN r5 -1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x80000000
+  #_ REGISTER_OUT r5 -1
+
+test_divwu_12_constant:
+  li r4, 1
+  sldi r4, r4, 31
+  li r5, -1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x80000000
+  #_ REGISTER_OUT r5 -1

src/xenia/cpu/frontend/testing/instr_eqv.s

@@ -0,0 +1,119 @@
+test_eqv_1:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 1
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_eqv_1_constant:
+  li r4, 0
+  li r5, 1
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_eqv_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+
+test_eqv_2_constant:
+  li r4, -1
+  li r5, 0
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+
+test_eqv_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_eqv_3_constant:
+  li r4, -1
+  li r5, -1
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_eqv_4:
+  #_ REGISTER_IN r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_IN r5 0xDEADBEEFDEADBEEF
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_OUT r5 0xDEADBEEFDEADBEEF
+
+test_eqv_4_constant:
+  lis r4, 0xDEAD
+  ori r4, r4, 0xBEEF
+  sldi r5, r4, 32
+  clrldi r4, r4, 32
+  or r4, r5, r4
+  mr r5, r4
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_OUT r5 0xDEADBEEFDEADBEEF
+
+test_eqv_5:
+  #_ REGISTER_IN r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEFDEADBEEF
+  #_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_eqv_5_constant:
+  lis r4, 0xDEAD
+  ori r4, r4, 0xBEEF
+  sldi r5, r4, 32
+  clrldi r4, r4, 32
+  or r4, r5, r4
+  li r5, -1
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEFDEADBEEF
+  #_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_eqv_6:
+  #_ REGISTER_IN r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_IN r5 0
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x2152411021524110
+  #_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_OUT r5 0
+
+test_eqv_6_constant:
+  lis r4, 0xDEAD
+  ori r4, r4, 0xBEEF
+  sldi r5, r4, 32
+  clrldi r4, r4, 32
+  or r4, r5, r4
+  li r5, 0
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x2152411021524110
+  #_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_OUT r5 0

src/xenia/cpu/frontend/testing/instr_extsb.s

@@ -0,0 +1,129 @@
+test_extsb_1:
+  #_ REGISTER_IN r4 0x0F
+  extsb r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0F
+  #_ REGISTER_OUT r4 0x0F
+
+test_extsb_1_constant:
+  li r4, 0x0F
+  extsb r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0F
+  #_ REGISTER_OUT r4 0x0F
+
+test_extsb_2:
+  #_ REGISTER_IN r4 0x7F
+  extsb r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x7F
+  #_ REGISTER_OUT r4 0x7F
+
+test_extsb_2_constant:
+  li r4, 0x7F
+  extsb r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x7F
+  #_ REGISTER_OUT r4 0x7F
+
+test_extsb_3:
+  #_ REGISTER_IN r4 0x80
+  extsb r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
+  #_ REGISTER_OUT r4 0x80
+
+test_extsb_3_constant:
+  li r4, 0x80
+  extsb r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
+  #_ REGISTER_OUT r4 0x80
+
+test_extsb_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFF080
+  extsb r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFF080
+
+test_extsb_4_constant:
+  li r4, 0xF7F
+  not r4, r4
+  extsb r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFF080
+
+test_extsb_cr_1:
+  #_ REGISTER_IN r4 0x0F
+  extsb. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0F
+  #_ REGISTER_OUT r4 0x0F
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extsb_cr_1_constant:
+  li r4, 0x0F
+  extsb. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0F
+  #_ REGISTER_OUT r4 0x0F
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extsb_cr_2:
+  #_ REGISTER_IN r4 0x7F
+  extsb. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7F
+  #_ REGISTER_OUT r4 0x7F
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extsb_cr_2_constant:
+  li r4, 0x7F
+  extsb. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7F
+  #_ REGISTER_OUT r4 0x7F
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extsb_cr_3:
+  #_ REGISTER_IN r4 0x80
+  extsb. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
+  #_ REGISTER_OUT r4 0x80
+  #_ REGISTER_OUT r12 0x80000000
+
+test_extsb_cr_3_constant:
+  li r4, 0x80
+  extsb. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
+  #_ REGISTER_OUT r4 0x80
+  #_ REGISTER_OUT r12 0x80000000
+
+test_extsb_cr_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFF080
+  extsb. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFF080
+  #_ REGISTER_OUT r12 0x80000000
+
+test_extsb_cr_4_constant:
+  li r4, 0xF7F
+  not r4, r4
+  extsb. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFF080
+  #_ REGISTER_OUT r12 0x80000000

src/xenia/cpu/frontend/testing/instr_extsh.s

@@ -0,0 +1,133 @@
+test_extsh_1:
+  #_ REGISTER_IN r4 0x0F
+  extsh r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0F
+  #_ REGISTER_OUT r4 0x0F
+
+test_extsh_1_constant:
+  li r4, 0x0F
+  extsh r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0F
+  #_ REGISTER_OUT r4 0x0F
+
+test_extsh_2:
+  #_ REGISTER_IN r4 0x7FFF
+  extsh r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x7FFF
+  #_ REGISTER_OUT r4 0x7FFF
+
+test_extsh_2_constant:
+  li r4, 0x7FFF
+  extsh r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x7FFF
+  #_ REGISTER_OUT r4 0x7FFF
+
+test_extsh_3:
+  #_ REGISTER_IN r4 0x8000
+  extsh r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
+  #_ REGISTER_OUT r4 0x8000
+
+test_extsh_3_constant:
+  li r4, 0x80
+  sldi r4, r4, 8
+  extsh r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
+  #_ REGISTER_OUT r4 0x8000
+
+test_extsh_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFF08000
+  extsh r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFF08000
+
+test_extsh_4_constant:
+  li r4, 0xF7F
+  not r4, r4
+  sldi r4, r4, 8
+  extsh r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFF08000
+
+test_extsh_cr_1:
+  #_ REGISTER_IN r4 0x0F
+  extsh. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0F
+  #_ REGISTER_OUT r4 0x0F
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extsh_cr_1_constant:
+  li r4, 0x0F
+  extsh. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0F
+  #_ REGISTER_OUT r4 0x0F
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extsh_cr_2:
+  #_ REGISTER_IN r4 0x7FFF
+  extsh. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFF
+  #_ REGISTER_OUT r4 0x7FFF
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extsh_cr_2_constant:
+  li r4, 0x7FFF
+  extsh. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFF
+  #_ REGISTER_OUT r4 0x7FFF
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extsh_cr_3:
+  #_ REGISTER_IN r4 0x8000
+  extsh. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
+  #_ REGISTER_OUT r4 0x8000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_extsh_cr_3_constant:
+  li r4, 0x80
+  sldi r4, r4, 8
+  extsh. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
+  #_ REGISTER_OUT r4 0x8000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_extsh_cr_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFF08000
+  extsh. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFF08000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_extsh_cr_4_constant:
+  li r4, 0xF7F
+  not r4, r4
+  sldi r4, r4, 8
+  extsh. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFF08000
+  #_ REGISTER_OUT r12 0x80000000

src/xenia/cpu/frontend/testing/instr_extsw.s

@@ -0,0 +1,135 @@
+test_extsw_1:
+  #_ REGISTER_IN r4 0x0F
+  extsw r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0F
+  #_ REGISTER_OUT r4 0x0F
+
+test_extsw_1_constant:
+  li r4, 0x0F
+  extsw r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0F
+  #_ REGISTER_OUT r4 0x0F
+
+test_extsw_2:
+  #_ REGISTER_IN r4 0x7FFFFFFF
+  extsw r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFF
+  #_ REGISTER_OUT r4 0x7FFFFFFF
+
+test_extsw_2_constant:
+  lis r4, 0x7FFF
+  ori r4, r4, 0xFFFF
+  extsw r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFF
+  #_ REGISTER_OUT r4 0x7FFFFFFF
+
+test_extsw_3:
+  #_ REGISTER_IN r4 0x80000000
+  extsw r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+  #_ REGISTER_OUT r4 0x80000000
+
+test_extsw_3_constant:
+  li r4, 0x80
+  sldi r4, r4, 24
+  extsw r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+  #_ REGISTER_OUT r4 0x80000000
+
+test_extsw_4:
+  #_ REGISTER_IN r4 0xFFFFFFF080000000
+  extsw r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+  #_ REGISTER_OUT r4 0xFFFFFFF080000000
+
+test_extsw_4_constant:
+  li r4, 0xF7F
+  not r4, r4
+  sldi r4, r4, 24
+  extsw r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+  #_ REGISTER_OUT r4 0xFFFFFFF080000000
+
+test_extsw_cr_1:
+  #_ REGISTER_IN r4 0x0F
+  extsw. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0F
+  #_ REGISTER_OUT r4 0x0F
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extsw_cr_1_constant:
+  li r4, 0x0F
+  extsw. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0F
+  #_ REGISTER_OUT r4 0x0F
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extsw_cr_2:
+  #_ REGISTER_IN r4 0x7FFFFFFF
+  extsw. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFF
+  #_ REGISTER_OUT r4 0x7FFFFFFF
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extsw_cr_2_constant:
+  lis r4, 0x7FFF
+  ori r4, r4, 0xFFFF
+  extsw. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFF
+  #_ REGISTER_OUT r4 0x7FFFFFFF
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extsw_cr_3:
+  #_ REGISTER_IN r4 0x80000000
+  extsw. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+  #_ REGISTER_OUT r4 0x80000000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_extsw_cr_3_constant:
+  li r4, 0x80
+  sldi r4, r4, 24
+  extsw. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+  #_ REGISTER_OUT r4 0x80000000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_extsw_cr_4:
+  #_ REGISTER_IN r4 0xFFFFFFF080000000
+  extsw. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+  #_ REGISTER_OUT r4 0xFFFFFFF080000000
+  #_ REGISTER_OUT r12 0x80000000
+
+test_extsw_cr_4_constant:
+  li r4, 0xF7F
+  not r4, r4
+  sldi r4, r4, 24
+  extsw. r3, r4
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+  #_ REGISTER_OUT r4 0xFFFFFFF080000000
+  #_ REGISTER_OUT r12 0x80000000

src/xenia/cpu/frontend/testing/instr_fabs.s

@@ -0,0 +1,41 @@
+test_fabs_1:
+  #_ REGISTER_IN f1 1.0
+  fabs f1, f1
+  blr
+  #_ REGISTER_OUT f1 1.0
+
+test_fabs_2:
+  #_ REGISTER_IN f1 -1.0
+  fabs f1, f1
+  blr
+  #_ REGISTER_OUT f1 1.0
+
+test_fabs_3:
+  #_ REGISTER_IN f1 -1234.0
+  fabs f1, f1
+  blr
+  #_ REGISTER_OUT f1 1234.0
+
+#test_fabs_cr_1:
+#  #_ REGISTER_IN f1 1.0
+#  fabs. f1, f1
+#  mfcr r12
+#  blr
+#  #_ REGISTER_OUT f1 1.0
+#  #_ REGISTER_OUT r12 0x04000000
+
+#test_fabs_cr_2:
+#  #_ REGISTER_IN f1 -1.0
+#  fabs. f1, f1
+#  mfcr r12
+#  blr
+#  #_ REGISTER_OUT f1 1.0
+#  #_ REGISTER_OUT r12 0x08000000
+
+#test_fabs_cr_3:
+#  #_ REGISTER_IN f1 -1234.0
+#  fabs. f1, f1
+#  mfcr r12
+#  blr
+#  #_ REGISTER_OUT f1 1234.0
+#  #_ REGISTER_OUT r12 0x08000000

src/xenia/cpu/frontend/testing/instr_fadd.s

@@ -0,0 +1,20 @@
+test_fadd_1:
+  #_ REGISTER_IN f1 1.0
+  #_ REGISTER_IN f2 2.0
+  fadd f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 3.0
+
+test_fadd_2:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 0.0
+  fadd f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 0.0
+
+test_fadd_3:
+  #_ REGISTER_IN f1 -200.0
+  #_ REGISTER_IN f2 200.0
+  fadd f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 0.0

src/xenia/cpu/frontend/testing/instr_fmadd.s

@@ -0,0 +1,47 @@
+test_fmadd_1:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 5.0
+  #_ REGISTER_IN f3 5.0
+  #_ REGISTER_IN f4 0.0
+  fmadd f1, f2, f3, f4
+  blr
+  #_ REGISTER_OUT f1 25.0
+  #_ REGISTER_OUT f2 5.0
+  #_ REGISTER_OUT f3 5.0
+  #_ REGISTER_OUT f4 0.0
+
+test_fmadd_2:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 5.0
+  #_ REGISTER_IN f3 0.0
+  #_ REGISTER_IN f4 15.0
+  fmadd f1, f2, f3, f4
+  blr
+  #_ REGISTER_OUT f1 15.0
+  #_ REGISTER_OUT f2 5.0
+  #_ REGISTER_OUT f3 0.0
+  #_ REGISTER_OUT f4 15.0
+
+test_fmadd_3:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 5.0
+  #_ REGISTER_IN f3 5.0
+  #_ REGISTER_IN f4 15.0
+  fmadd f1, f2, f3, f4
+  blr
+  #_ REGISTER_OUT f1 40.0
+  #_ REGISTER_OUT f2 5.0
+  #_ REGISTER_OUT f3 5.0
+  #_ REGISTER_OUT f4 15.0
+
+test_fmadd_4:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 9999.99
+  #_ REGISTER_IN f3 9999.99
+  #_ REGISTER_IN f4 9999.99
+  fmadd f1, f2, f3, f4
+  blr
+  #_ REGISTER_OUT f1 100009799.9901
+  #_ REGISTER_OUT f2 9999.99
+  #_ REGISTER_OUT f3 9999.99
+  #_ REGISTER_OUT f4 9999.99

src/xenia/cpu/frontend/testing/instr_fmadds.s

@@ -0,0 +1,47 @@
+test_fmadds_1:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 5.0
+  #_ REGISTER_IN f3 5.0
+  #_ REGISTER_IN f4 0.0
+  fmadds f1, f2, f3, f4
+  blr
+  #_ REGISTER_OUT f1 25.0
+  #_ REGISTER_OUT f2 5.0
+  #_ REGISTER_OUT f3 5.0
+  #_ REGISTER_OUT f4 0.0
+
+test_fmadds_2:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 5.0
+  #_ REGISTER_IN f3 0.0
+  #_ REGISTER_IN f4 15.0
+  fmadds f1, f2, f3, f4
+  blr
+  #_ REGISTER_OUT f1 15.0
+  #_ REGISTER_OUT f2 5.0
+  #_ REGISTER_OUT f3 0.0
+  #_ REGISTER_OUT f4 15.0
+
+test_fmadds_3:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 5.0
+  #_ REGISTER_IN f3 5.0
+  #_ REGISTER_IN f4 15.0
+  fmadds f1, f2, f3, f4
+  blr
+  #_ REGISTER_OUT f1 40.0
+  #_ REGISTER_OUT f2 5.0
+  #_ REGISTER_OUT f3 5.0
+  #_ REGISTER_OUT f4 15.0
+
+test_fmadds_4:
+  #_ REGISTER_IN f1 0.0
+  #_ REGISTER_IN f2 9999.99
+  #_ REGISTER_IN f3 9999.99
+  #_ REGISTER_IN f4 9999.99
+  fmadds f1, f2, f3, f4
+  blr
+  #_ REGISTER_OUT f1 100009800.0
+  #_ REGISTER_OUT f2 9999.99
+  #_ REGISTER_OUT f3 9999.99
+  #_ REGISTER_OUT f4 9999.99

src/xenia/cpu/frontend/testing/instr_fmul.s

@@ -0,0 +1,20 @@
+test_fmul_1:
+  #_ REGISTER_IN f1 5.0
+  #_ REGISTER_IN f2 5.0
+  fmul f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 25.0
+
+test_fmul_2:
+  #_ REGISTER_IN f1 5.0
+  #_ REGISTER_IN f2 0.0
+  fmul f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 0.0
+
+test_fmul_3:
+  #_ REGISTER_IN f1 -2.0
+  #_ REGISTER_IN f2 2.0
+  fmul f3, f1, f2
+  blr
+  #_ REGISTER_OUT f3 -4.0

src/xenia/cpu/frontend/testing/instr_fnabs.s

@@ -0,0 +1,5 @@
+test_fnabs_1:
+  #_ REGISTER_IN f1 0x400C000000000000
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f2 0xC00C000000000000

src/xenia/cpu/frontend/testing/instr_frsqrte.s

@@ -0,0 +1,19 @@
+test_frsqrte_1:
+  #_ REGISTER_IN f1 1.0
+  frsqrte f1, f1
+  blr
+  #_ REGISTER_OUT f1 0.99975585937500000
+  # want: 0.97
+
+test_frsqrte_2:
+  #_ REGISTER_IN f1 64.0
+  frsqrte f1, f1
+  blr
+  #_ REGISTER_OUT f1 0.12496948242187500
+
+test_frsqrte_3:
+  #_ REGISTER_IN f1 0.5
+  frsqrte f1, f1
+  blr
+  #_ REGISTER_OUT f1 1.4138183593750000
+  # want: 1.375

src/xenia/cpu/frontend/testing/instr_fsel.s

@@ -0,0 +1,32 @@
+test_fsel_1:
+  #_ REGISTER_IN f2 2.0
+  #_ REGISTER_IN f3 3.0
+  #_ REGISTER_IN f4 4.0
+  fsel f1, f2, f3, f4
+  blr
+  #_ REGISTER_OUT f1 3.0
+  #_ REGISTER_OUT f2 2.0
+  #_ REGISTER_OUT f3 3.0
+  #_ REGISTER_OUT f4 4.0
+
+test_fsel_2:
+  #_ REGISTER_IN f2 -2.0
+  #_ REGISTER_IN f3 3.0
+  #_ REGISTER_IN f4 4.0
+  fsel f1, f2, f3, f4
+  blr
+  #_ REGISTER_OUT f1 4.0
+  #_ REGISTER_OUT f2 -2.0
+  #_ REGISTER_OUT f3 3.0
+  #_ REGISTER_OUT f4 4.0
+
+test_fsel_3:
+  #_ REGISTER_IN f2 0.0
+  #_ REGISTER_IN f3 3.0
+  #_ REGISTER_IN f4 4.0
+  fsel f1, f2, f3, f4
+  blr
+  #_ REGISTER_OUT f1 3.0
+  #_ REGISTER_OUT f2 0.0
+  #_ REGISTER_OUT f3 3.0
+  #_ REGISTER_OUT f4 4.0

src/xenia/cpu/frontend/testing/instr_fsqrt.s

@@ -0,0 +1,17 @@
+test_fsqrt_1:
+  #_ REGISTER_IN f1 1.0
+  fsqrt f1, f1
+  blr
+  #_ REGISTER_OUT f1 1.0000000000000000
+
+test_fsqrt_2:
+  #_ REGISTER_IN f1 64.0
+  fsqrt f1, f1
+  blr
+  #_ REGISTER_OUT f1 8.0000000000000000
+
+test_fsqrt_3:
+  #_ REGISTER_IN f1 0.5
+  fsqrt f1, f1
+  blr
+  #_ REGISTER_OUT f1 0.70710678118654757

src/xenia/cpu/frontend/testing/instr_lvexx.s

@@ -0,0 +1,95 @@
+test_lvebx_1:
+  #_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  #_ REGISTER_IN r4 0x00001000
+  lvebx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvebx_1_constant:
+  #_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  li r4, 0x00001000
+  lvebx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvebx_2:
+  #_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  #_ REGISTER_IN r4 0x00001004
+  lvebx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x00001004
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvebx_2_constant:
+  #_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  li r4, 0x00001004
+  lvebx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x00001004
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvehx_1:
+  #_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  #_ REGISTER_IN r4 0x00001000
+  lvehx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvehx_1_constant:
+  #_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  li r4, 0x00001000
+  lvehx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvehx_2:
+  #_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  #_ REGISTER_IN r4 0x00001004
+  lvehx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x00001004
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvehx_2_constant:
+  #_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  li r4, 0x00001004
+  lvehx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x00001004
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvewx_1:
+  #_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  #_ REGISTER_IN r4 0x00001000
+  lvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvewx_1_constant:
+  #_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  li r4, 0x00001000
+  lvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvewx_2:
+  #_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  #_ REGISTER_IN r4 0x00001004
+  lvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x00001004
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvewx_2_constant:
+  #_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  li r4, 0x00001004
+  lvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x00001004
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]

src/xenia/cpu/frontend/testing/instr_lvl.s

@@ -0,0 +1,15 @@
+test_lvl_1:
+  #_ MEMORY_IN 00001077 0a 0b 0c 0d 0e 0f 10 13 0c 0d 0e 10 11 12 13 14 ff ff ff ff ff ff
+  #_ REGISTER_IN r4 0x1077
+  lvlx v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1077
+  #_ REGISTER_OUT v3 [0A0B0C0D, 0E0F1013, 0C000000, 00000000]
+
+test_lvl_1_constant:
+  #_ MEMORY_IN 00001077 0a 0b 0c 0d 0e 0f 10 13 0c 0d 0e 10 11 12 13 14 ff ff ff ff ff ff
+  li r4, 0x1077
+  lvlx v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1077
+  #_ REGISTER_OUT v3 [0A0B0C0D, 0E0F1013, 0C000000, 00000000]

src/xenia/cpu/frontend/testing/instr_lvr.s

@@ -0,0 +1,19 @@
+test_lvr_1:
+  #_ MEMORY_IN 000010B0 090A0A0B 0C0F120A 0B0C0D0E 0F10130C 0D0E1011 121314FF FFFFFFFF
+  #_ REGISTER_IN r4 0x10B7
+  #_ REGISTER_IN r5 0x10
+  lvrx v3, r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x10B7
+  #_ REGISTER_OUT r5 0x10
+  #_ REGISTER_OUT v3 [00000000, 00000000, 000D0E10, 11121314]
+
+test_lvr_1_constant:
+  #_ MEMORY_IN 000010B0 090A0A0B 0C0F120A 0B0C0D0E 0F10130C 0D0E1011 121314FF FFFFFFFF
+  li r4, 0x10B7
+  li r5, 0x10
+  lvrx v3, r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x10B7
+  #_ REGISTER_OUT r5 0x10
+  #_ REGISTER_OUT v3 [00000000, 00000000, 000D0E10, 11121314]

src/xenia/cpu/frontend/testing/instr_lvsl.s

@@ -0,0 +1,41 @@
+test_lvsl_1:
+  #_ REGISTER_IN r4 0x1070
+  lvsl v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1070
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvsl_1_constant:
+  li r4, 0x1070
+  lvsl v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1070
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvsl_2:
+  #_ REGISTER_IN r4 0x1071
+  lvsl v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1071
+  #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
+
+test_lvsl_2_constant:
+  li r4, 0x1071
+  lvsl v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1071
+  #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
+
+test_lvsl_3:
+  #_ REGISTER_IN r4 0x107F
+  lvsl v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x107F
+  #_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E]
+
+test_lvsl_3_constant:
+  li r4, 0x107F
+  lvsl v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x107F
+  #_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E]

src/xenia/cpu/frontend/testing/instr_lvsr.s

@@ -0,0 +1,41 @@
+test_lvsr_1:
+  #_ REGISTER_IN r4 0x1070
+  lvsr v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1070
+  #_ REGISTER_OUT v3 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+
+test_lvsr_1_constant:
+  li r4, 0x1070
+  lvsr v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1070
+  #_ REGISTER_OUT v3 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+
+test_lvsr_2:
+  #_ REGISTER_IN r4 0x1071
+  lvsr v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1071
+  #_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E]
+
+test_lvsr_2_constant:
+  li r4, 0x1071
+  lvsr v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1071
+  #_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E]
+
+test_lvsr_3:
+  #_ REGISTER_IN r4 0x107F
+  lvsr v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x107F
+  #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
+
+test_lvsr_3_constant:
+  li r4, 0x107F
+  lvsr v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x107F
+  #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]

src/xenia/cpu/frontend/testing/instr_mulhd.s

@@ -0,0 +1,89 @@
+test_mulhd_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0
+  mulhd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_mulhd_1_constant:
+  li r4, 1
+  li r5, 0
+  mulhd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_mulhd_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  mulhd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhd_2_constant:
+  li r4, -1
+  li r5, 1
+  mulhd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhd_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 2
+  mulhd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 2
+
+test_mulhd_3_constant:
+  li r4, -1
+  li r5, 2
+  mulhd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 2
+
+test_mulhd_4:
+  #_ REGISTER_IN r4 0x8000000000000000
+  #_ REGISTER_IN r5 1
+  mulhd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x8000000000000000
+  #_ REGISTER_OUT r5 1
+
+test_mulhd_4_constant:
+  li r5, 1
+  sldi r4, r5, 63
+  mulhd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x8000000000000000
+  #_ REGISTER_OUT r5 1
+
+test_mulhd_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  mulhd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_mulhd_5_constant:
+  li r4, -1
+  li r5, -1
+  mulhd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF

src/xenia/cpu/frontend/testing/instr_mulhdu.s

@@ -0,0 +1,89 @@
+test_mulhdu_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0
+  mulhdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_mulhdu_1_constant:
+  li r4, 1
+  li r5, 0
+  mulhdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_mulhdu_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  mulhdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhdu_2_constant:
+  li r4, -1
+  li r5, 1
+  mulhdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhdu_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 2
+  mulhdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 2
+
+test_mulhdu_3_constant:
+  li r4, -1
+  li r5, 2
+  mulhdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 2
+
+test_mulhdu_4:
+  #_ REGISTER_IN r4 0x8000000000000000
+  #_ REGISTER_IN r5 1
+  mulhdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x8000000000000000
+  #_ REGISTER_OUT r5 1
+
+test_mulhdu_4_constant:
+  li r5, 1
+  sldi r4, r5, 63
+  mulhdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x8000000000000000
+  #_ REGISTER_OUT r5 1
+
+test_mulhdu_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  mulhdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_mulhdu_5_constant:
+  li r4, -1
+  li r5, -1
+  mulhdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF

src/xenia/cpu/frontend/testing/instr_mulhw.s

@@ -0,0 +1,113 @@
+test_mulhw_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0
+  mulhw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_mulhw_1_constant:
+  li r4, 1
+  li r5, 0
+  mulhw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_mulhw_2:
+  #_ REGISTER_IN r4 0x00000000FFFFFFFF
+  #_ REGISTER_IN r5 1
+  mulhw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhw_2_constant:
+  li r4, -1
+  clrldi r4, r4, 32
+  li r5, 1
+  mulhw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhw_3:
+  #_ REGISTER_IN r4 0x00000001FFFFFFFF
+  #_ REGISTER_IN r5 1
+  mulhw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x00000001FFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhw_3_constant:
+  li r4, -1
+  clrldi r4, r4, 31
+  li r5, 1
+  mulhw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x00000001FFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhw_4:
+  #_ REGISTER_IN r4 0x800000007FFFFFFF
+  #_ REGISTER_IN r5 1
+  mulhw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x800000007FFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhw_4_constant:
+  li r4, -1
+  clrldi r4, r4, 33
+  li r5, 1
+  sldi r5, r5, 63
+  or r4, r4, r5
+  li r5, 1
+  mulhw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x800000007FFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhw_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  mulhw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhw_5_constant:
+  li r4, -1
+  li r5, 1
+  mulhw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhw_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  mulhw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_mulhw_6_constant:
+  li r4, -1
+  li r5, -1
+  mulhw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF

src/xenia/cpu/frontend/testing/instr_mulhwu.s

@@ -0,0 +1,113 @@
+test_mulhwu_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0
+  mulhwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_mulhwu_1_constant:
+  li r4, 1
+  li r5, 0
+  mulhwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_mulhwu_2:
+  #_ REGISTER_IN r4 0x00000000FFFFFFFF
+  #_ REGISTER_IN r5 1
+  mulhwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhwu_2_constant:
+  li r4, -1
+  clrldi r4, r4, 32
+  li r5, 1
+  mulhwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhwu_3:
+  #_ REGISTER_IN r4 0x00000001FFFFFFFF
+  #_ REGISTER_IN r5 1
+  mulhwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x00000001FFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhwu_3_constant:
+  li r4, -1
+  clrldi r4, r4, 31
+  li r5, 1
+  mulhwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x00000001FFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhwu_4:
+  #_ REGISTER_IN r4 0x800000007FFFFFFF
+  #_ REGISTER_IN r5 1
+  mulhwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x800000007FFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhwu_4_constant:
+  li r4, -1
+  clrldi r4, r4, 33
+  li r5, 1
+  sldi r5, r5, 63
+  or r4, r4, r5
+  li r5, 1
+  mulhwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x800000007FFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhwu_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  mulhwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhwu_5_constant:
+  li r4, -1
+  li r5, 1
+  mulhwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulhwu_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  mulhwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_mulhwu_6_constant:
+  li r4, -1
+  li r5, -1
+  mulhwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF

src/xenia/cpu/frontend/testing/instr_mulld.s

@@ -0,0 +1,143 @@
+test_mulld_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_mulld_1_constant:
+  li r4, 1
+  li r5, 0
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_mulld_2:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 1
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 1
+
+test_mulld_2_constant:
+  li r4, 1
+  li r5, 1
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 1
+
+test_mulld_3:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 -1
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 -1
+
+test_mulld_3_constant:
+  li r4, 1
+  li r5, -1
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 -1
+
+test_mulld_4:
+  #_ REGISTER_IN r4 123
+  #_ REGISTER_IN r5 -1
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 -123
+  #_ REGISTER_OUT r4 123
+  #_ REGISTER_OUT r5 -1
+
+test_mulld_4_constant:
+  li r4, 123
+  li r5, -1
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 -123
+  #_ REGISTER_OUT r4 123
+  #_ REGISTER_OUT r5 -1
+
+test_mulld_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulld_5_constant:
+  li r4, -1
+  li r5, 1
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mulld_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 2
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 2
+
+test_mulld_6_constant:
+  li r4, -1
+  li r5, 2
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 2
+
+test_mulld_7:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 -1
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 -1
+
+test_mulld_7_constant:
+  li r4, 1
+  li r5, -1
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 -1
+
+test_mulld_8:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 -1
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 -1
+
+test_mulld_8_constant:
+  li r4, -1
+  li r5, -1
+  mulld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 -1

src/xenia/cpu/frontend/testing/instr_mulli.s

@@ -0,0 +1,111 @@
+test_mulli_1:
+  #_ REGISTER_IN r4 1
+  mulli r3, r4, 0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_mulli_1_constant:
+  li r4, 1
+  mulli r3, r4, 0
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_mulli_2:
+  #_ REGISTER_IN r4 1
+  mulli r3, r4, 1
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+
+test_mulli_2_constant:
+  li r4, 1
+  mulli r3, r4, 1
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+
+test_mulli_3:
+  #_ REGISTER_IN r4 1
+  mulli r3, r4, -1
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 1
+
+test_mulli_3_constant:
+  li r4, 1
+  mulli r3, r4, -1
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 1
+
+test_mulli_4:
+  #_ REGISTER_IN r4 123
+  mulli r3, r4, -1
+  blr
+  #_ REGISTER_OUT r3 -123
+  #_ REGISTER_OUT r4 123
+
+test_mulli_4_constant:
+  li r4, 123
+  mulli r3, r4, -1
+  blr
+  #_ REGISTER_OUT r3 -123
+  #_ REGISTER_OUT r4 123
+
+test_mulli_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  mulli r3, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_mulli_5_constant:
+  li r4, -1
+  mulli r3, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_mulli_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  mulli r3, r4, 2
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_mulli_6_constant:
+  li r4, -1
+  mulli r3, r4, 2
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_mulli_7:
+  #_ REGISTER_IN r4 1
+  mulli r3, r4, -1
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 1
+
+test_mulli_7_constant:
+  li r4, 1
+  mulli r3, r4, -1
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 1
+
+test_mulli_8:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  mulli r3, r4, -1
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_mulli_8_constant:
+  li r4, -1
+  mulli r3, r4, -1
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF

src/xenia/cpu/frontend/testing/instr_mullw.s

@@ -0,0 +1,200 @@
+test_mullw_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_mullw_1_constant:
+  li r4, 1
+  li r5, 0
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_mullw_2:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 1
+
+test_mullw_2_constant:
+  li r4, 1
+  li r5, 1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 1
+
+test_mullw_3:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 -1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 -1
+
+test_mullw_3_constant:
+  li r4, 1
+  li r5, -1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 -1
+
+test_mullw_4:
+  #_ REGISTER_IN r4 123
+  #_ REGISTER_IN r5 -1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 -123
+  #_ REGISTER_OUT r4 123
+  #_ REGISTER_OUT r5 -1
+
+test_mullw_4_constant:
+  li r4, 123
+  li r5, -1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 -123
+  #_ REGISTER_OUT r4 123
+  #_ REGISTER_OUT r5 -1
+
+test_mullw_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mullw_5_constant:
+  li r4, -1
+  li r5, 1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_mullw_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 2
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 2
+
+test_mullw_6_constant:
+  li r4, -1
+  li r5, 2
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 2
+
+test_mullw_7:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 -1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 -1
+
+test_mullw_7_constant:
+  li r4, 1
+  li r5, -1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 -1
+
+test_mullw_8:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 -1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 -1
+
+test_mullw_8_constant:
+  li r4, -1
+  li r5, -1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 -1
+
+test_mullw_9:
+  #_ REGISTER_IN r4 0xFFFFFFFF00000000
+  #_ REGISTER_IN r5 1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFF00000000
+  #_ REGISTER_OUT r5 1
+
+test_mullw_9_constant:
+  li r4, -1
+  sldi r4, r4, 32
+  li r5, 1
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFF00000000
+  #_ REGISTER_OUT r5 1
+
+test_mullw_10:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0xFFFFFFFF00000000
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFF00000000
+
+test_mullw_10_constant:
+  li r4, 1
+  li r5, -1
+  sldi r5, r5, 32
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFF00000000
+
+test_mullw_11:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0x000000007FFFFFFF
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+test_mullw_11_constant:
+  li r4, 1
+  li r5, -1
+  clrldi r5, r5, 33
+  mullw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF

src/xenia/cpu/frontend/testing/instr_neg.s

@@ -0,0 +1,37 @@
+test_neg_1:
+  #_ REGISTER_IN r3 0x0000000080000000
+  neg r3, r3
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+
+test_neg_1_constant:
+  li r3, 1
+  sldi r3, r3, 31
+  neg r3, r3
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+
+test_neg_2:
+  #_ REGISTER_IN r3 0x8000000000000000
+  neg r3, r3
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+
+test_neg_2_constant:
+  li r3, 1
+  sldi r3, r3, 63
+  neg r3, r3
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+
+test_neg_3:
+  #_ REGISTER_IN r3 0x0000000000000005
+  neg r3, r3
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFB
+
+test_neg_3_constant:
+  li r3, 5
+  neg r3, r3
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFB

src/xenia/cpu/frontend/testing/instr_nor.s

@@ -0,0 +1,20 @@
+test_nor_cr_1:
+  #_ REGISTER_IN r3 0x00000000FFFFFFFF
+  nor. r3, r3, r3
+  li r3, 0
+  bne .nor_cr_1_ne
+  li r3, 1
+  .nor_cr_1_ne:
+  blr
+  #_ REGISTER_OUT r3 1
+
+test_nor_cr_1_constant:
+  li r3, -1
+  clrldi r3, r3, 32
+  nor. r3, r3, r3
+  li r3, 0
+  bne .nor_cr_1_constant_ne
+  li r3, 1
+  .nor_cr_1_constant_ne:
+  blr
+  #_ REGISTER_OUT r3 1

src/xenia/cpu/frontend/testing/instr_ori.s

@@ -0,0 +1,42 @@
+.macro make_test_constant dest
+  lis \dest, 0xDEAD
+  ori \dest, \dest, 0xBEEF
+  sldi \dest, \dest, 32
+.endm
+
+test_ori_1:
+  #_ REGISTER_IN r4 0xDEADBEEF00000000
+
+  ori r3, r4, 0xFEDC
+
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEF0000FEDC
+  #_ REGISTER_OUT r4 0xDEADBEEF00000000
+
+test_ori_1_constant:
+  make_test_constant r4
+  ori r3, r4, 0xFEDC
+
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEF0000FEDC
+  #_ REGISTER_OUT r4 0xDEADBEEF00000000
+
+test_ori_2:
+  #_ REGISTER_IN r4 0xDEADBEEF10000000
+
+  ori r3, r4, 0xFEDC
+
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEF1000FEDC
+  #_ REGISTER_OUT r4 0xDEADBEEF10000000
+
+test_ori_2_constant:
+  make_test_constant r4
+  lis r3, 0x1000
+  or r4, r4, r3
+
+  ori r3, r4, 0xFEDC
+
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEF1000FEDC
+  #_ REGISTER_OUT r4 0xDEADBEEF10000000

src/xenia/cpu/frontend/testing/instr_rldicl.s

@@ -0,0 +1,221 @@
+.macro make_test_constant dest
+  lis \dest, 0x0123
+  ori \dest, \dest, 0x4567
+  sldi \dest, \dest, 32
+  lis r3, 0x89AB
+  ori r3, r3, 0xCDEF
+  clrldi r3, r3, 32
+  or \dest, \dest, r3
+.endm
+
+test_rldicl_1:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicl r3, r4, 24, 0
+  blr
+  #_ REGISTER_OUT r3 0x6789abcdef012345
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_1_constant:
+  make_test_constant r4
+  rldicl r3, r4, 24, 0
+  blr
+  #_ REGISTER_OUT r3 0x6789abcdef012345
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_2:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicl r3, r4, 24, 8
+  blr
+  #_ REGISTER_OUT r3 0x0089abcdef012345
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_2_constant:
+  make_test_constant r4
+  rldicl r3, r4, 24, 8
+  blr
+  #_ REGISTER_OUT r3 0x0089abcdef012345
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_3:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicl r3, r4, 24, 63
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_3_constant:
+  make_test_constant r4
+  rldicl r3, r4, 24, 63
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_4:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicl r3, r4, 0, 0
+  blr
+  #_ REGISTER_OUT r3 0x0123456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_4_constant:
+  make_test_constant r4
+  rldicl r3, r4, 0, 0
+  blr
+  #_ REGISTER_OUT r3 0x0123456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_5:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicl r3, r4, 0, 63
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_5_constant:
+  make_test_constant r4
+  rldicl r3, r4, 0, 63
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_6:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicl r3, r4, 0, 8
+  blr
+  #_ REGISTER_OUT r3 0x0023456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_6_constant:
+  make_test_constant r4
+  rldicl r3, r4, 0, 8
+  blr
+  #_ REGISTER_OUT r3 0x0023456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_7:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicl r3, r4, 63, 0
+  blr
+  #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_7_constant:
+  make_test_constant r4
+  rldicl r3, r4, 63, 0
+  blr
+  #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_8:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicl r3, r4, 63, 63
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_8_constant:
+  make_test_constant r4
+  rldicl r3, r4, 63, 63
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_9:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicl r3, r4, 31, 0
+  blr
+  #_ REGISTER_OUT r3 0xc4d5e6f78091a2b3
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_9_constant:
+  make_test_constant r4
+  rldicl r3, r4, 31, 0
+  blr
+  #_ REGISTER_OUT r3 0xc4d5e6f78091a2b3
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicl_10:
+  #_ REGISTER_IN r4 0x16300000
+  rldicl r3, r4, 58, 6
+  blr
+  #_ REGISTER_OUT r3 0x58C000
+  #_ REGISTER_OUT r4 0x16300000
+
+test_rldicl_10_constant:
+  lis r4, 0x1630
+  rldicl r3, r4, 58, 6
+  blr
+  #_ REGISTER_OUT r3 0x58C000
+  #_ REGISTER_OUT r4 0x16300000
+
+test_srdi_1:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  srdi r3, r3, 0
+  srdi r4, r4, 0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_srdi_1_constant:
+  make_test_constant r4
+  li r3, -1
+  srdi r3, r3, 0
+  srdi r4, r4, 0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_srdi_2:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  srdi r3, r3, 1
+  srdi r4, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0x7fffffffffffffff
+  #_ REGISTER_OUT r4 0x0091a2b3c4d5e6f7
+
+test_srdi_2_constant:
+  make_test_constant r4
+  li r3, -1
+  srdi r3, r3, 1
+  srdi r4, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0x7fffffffffffffff
+  #_ REGISTER_OUT r4 0x0091a2b3c4d5e6f7
+
+test_srdi_3:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  srdi r3, r3, 32
+  srdi r4, r4, 32
+  blr
+  #_ REGISTER_OUT r3 0x00000000ffffffff
+  #_ REGISTER_OUT r4 0x0000000001234567
+
+test_srdi_3_constant:
+  make_test_constant r4
+  li r3, -1
+  srdi r3, r3, 32
+  srdi r4, r4, 32
+  blr
+  #_ REGISTER_OUT r3 0x00000000ffffffff
+  #_ REGISTER_OUT r4 0x0000000001234567
+
+test_srdi_4:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  srdi r3, r3, 63
+  srdi r4, r4, 63
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000000000
+
+test_srdi_4_constant:
+  make_test_constant r4
+  li r3, -1
+  srdi r3, r3, 63
+  srdi r4, r4, 63
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000000000

src/xenia/cpu/frontend/testing/instr_rldicr.s

@@ -0,0 +1,207 @@
+.macro make_test_constant dest
+  lis \dest, 0x0123
+  ori \dest, \dest, 0x4567
+  sldi \dest, \dest, 32
+  lis r3, 0x89AB
+  ori r3, r3, 0xCDEF
+  clrldi r3, r3, 32
+  or \dest, \dest, r3
+.endm
+
+test_rldicr_1:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicr r3, r4, 24, 0
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_1_constant:
+  make_test_constant r4
+  rldicr r3, r4, 24, 0
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_2:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicr r3, r4, 24, 8
+  blr
+  #_ REGISTER_OUT r3 0x6780000000000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_2_constant:
+  make_test_constant r4
+  rldicr r3, r4, 24, 8
+  blr
+  #_ REGISTER_OUT r3 0x6780000000000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_3:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicr r3, r4, 24, 63
+  blr
+  #_ REGISTER_OUT r3 0x6789abcdef012345
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_3_constant:
+  make_test_constant r4
+  rldicr r3, r4, 24, 63
+  blr
+  #_ REGISTER_OUT r3 0x6789abcdef012345
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_4:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicr r3, r4, 0, 0
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_4_constant:
+  make_test_constant r4
+  rldicr r3, r4, 0, 0
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_5:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicr r3, r4, 0, 63
+  blr
+  #_ REGISTER_OUT r3 0x0123456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_5_constant:
+  make_test_constant r4
+  rldicr r3, r4, 0, 63
+  blr
+  #_ REGISTER_OUT r3 0x0123456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_6:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicr r3, r4, 0, 8
+  blr
+  #_ REGISTER_OUT r3 0x0100000000000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_6_constant:
+  make_test_constant r4
+  rldicr r3, r4, 0, 8
+  blr
+  #_ REGISTER_OUT r3 0x0100000000000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_7:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicr r3, r4, 63, 0
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_7_constant:
+  make_test_constant r4
+  rldicr r3, r4, 63, 0
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_8:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicr r3, r4, 63, 63
+  blr
+  #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_8_constant:
+  make_test_constant r4
+  rldicr r3, r4, 63, 63
+  blr
+  #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_9:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldicr r3, r4, 31, 0
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldicr_9_constant:
+  make_test_constant r4
+  rldicr r3, r4, 31, 0
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_sldi_1:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  sldi r3, r3, 0
+  sldi r4, r4, 0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_sldi_1_constant:
+  make_test_constant r4
+  li r3, -1
+  sldi r3, r3, 0
+  sldi r4, r4, 0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_sldi_2:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  sldi r3, r3, 1
+  sldi r4, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0x02468acf13579bde
+
+test_sldi_2_constant:
+  make_test_constant r4
+  li r3, -1
+  sldi r3, r3, 1
+  sldi r4, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0x02468acf13579bde
+
+test_sldi_3:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  sldi r3, r3, 32
+  sldi r4, r4, 32
+  blr
+  #_ REGISTER_OUT r3 0xffffffff00000000
+  #_ REGISTER_OUT r4 0x89abcdef00000000
+
+test_sldi_3_constant:
+  make_test_constant r4
+  li r3, -1
+  sldi r3, r3, 32
+  sldi r4, r4, 32
+  blr
+  #_ REGISTER_OUT r3 0xffffffff00000000
+  #_ REGISTER_OUT r4 0x89abcdef00000000
+
+test_sldi_4:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  sldi r3, r3, 63
+  sldi r4, r4, 63
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+  #_ REGISTER_OUT r4 0x8000000000000000
+
+test_sldi_4_constant:
+  make_test_constant r4
+  li r3, -1
+  sldi r3, r3, 63
+  sldi r4, r4, 63
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+  #_ REGISTER_OUT r4 0x8000000000000000

src/xenia/cpu/frontend/testing/instr_rlwimi.s

@@ -0,0 +1,25 @@
+.macro make_test_constant dest, a, b, c, d
+  lis \dest, \a
+  ori \dest, \dest, \b
+  sldi \dest, \dest, 32
+  lis r3, \c
+  ori r3, r3, \d
+  clrldi r3, r3, 32
+  or \dest, \dest, r3
+.endm
+
+test_rlwimi:
+  #_ REGISTER_IN r4 0xCAFEBABE90003000
+  #_ REGISTER_IN r6 0xDEADBEEF00000003
+  rlwimi r6, r4, 2, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r4 0xCAFEBABE90003000
+  #_ REGISTER_OUT r6 0xDEADBEEF4000C003
+
+test_rlwimi_constant:
+  make_test_constant r4, 0xCAFE, 0xBABE, 0x9000, 0x3000
+  make_test_constant r6, 0xDEAD, 0xBEEF, 0x0000, 0x0003
+  rlwimi r6, r4, 2, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r4 0xCAFEBABE90003000
+  #_ REGISTER_OUT r6 0xDEADBEEF4000C003

src/xenia/cpu/frontend/testing/instr_rlwinm.s

@@ -0,0 +1,231 @@
+test_extrwi_1:
+  # extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
+  #_ REGISTER_IN r5 0x30
+  # rlwinm r7, r5, 29, 28, 31
+  extrwi r7, r5, 4, 25
+  blr
+  #_ REGISTER_OUT r5 0x30
+  #_ REGISTER_OUT r7 0x06
+
+test_extrwi_1_constant:
+  # extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
+  li r5, 0x30
+  # rlwinm r7, r5, 29, 28, 31
+  extrwi r7, r5, 4, 25
+  blr
+  #_ REGISTER_OUT r5 0x30
+  #_ REGISTER_OUT r7 0x06
+
+test_extrwi_2:
+  #_ REGISTER_IN r5 0xFFFFFFFF01234567
+  extrwi r7, r5, 16, 10
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF01234567
+  #_ REGISTER_OUT r7 0x0000000000008D15
+
+test_extrwi_2_constant:
+  li r5, -1
+  sldi r5, r5, 32
+  oris r5, r5, 0x0123
+  ori r5, r5, 0x4567
+  extrwi r7, r5, 16, 10
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF01234567
+  #_ REGISTER_OUT r7 0x0000000000008D15
+
+test_rlwinm_1:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 24, 8, 15
+  blr
+  #_ REGISTER_OUT r3 0x00120000
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_1_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  rlwinm r3, r4, 24, 8, 15
+  blr
+  #_ REGISTER_OUT r3 0x00120000
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_2:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 4, 0, 27
+  blr
+  #_ REGISTER_OUT r3 0x23456780
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_2_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  rlwinm r3, r4, 4, 0, 27
+  blr
+  #_ REGISTER_OUT r3 0x23456780
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_3:
+  #_ REGISTER_IN r4 0x90003000
+  rlwinm r3, r4, 2, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0x4000C000
+  #_ REGISTER_OUT r4 0x90003000
+
+test_rlwinm_3_constant:
+  lis r4, 0x9000
+  ori r4, r4, 0x3000
+  clrldi r4, r4, 32
+  rlwinm r3, r4, 2, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0x4000C000
+  #_ REGISTER_OUT r4 0x90003000
+
+test_rlwinm_4:
+  #_ REGISTER_IN r4 0xB0043000
+  rlwinm. r3, r4, 2, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0xC010C000
+  #_ REGISTER_OUT r4 0xB0043000
+  # CRF = 0x8
+
+test_rlwinm_4_constant:
+  lis r4, 0xB004
+  ori r4, r4, 0x3000
+  clrldi r4, r4, 32
+  rlwinm. r3, r4, 2, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0xC010C000
+  #_ REGISTER_OUT r4 0xB0043000
+  # CRF = 0x8
+
+test_rlwinm_5:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 0, 5, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0x02345678
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_5_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  rlwinm r3, r4, 0, 5, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0x02345678
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_6:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 0, 0, 31
+  blr
+  #_ REGISTER_OUT r3 0x12345678
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_6_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  rlwinm r3, r4, 0, 0, 31
+  blr
+  #_ REGISTER_OUT r3 0x12345678
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_7:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 0, 0, 16
+  blr
+  #_ REGISTER_OUT r3 0x12340000
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_7_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  rlwinm r3, r4, 0, 0, 16
+  blr
+  #_ REGISTER_OUT r3 0x12340000
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_8:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 0, 16, 31
+  blr
+  #_ REGISTER_OUT r3 0x00005678
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_8_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  rlwinm r3, r4, 0, 16, 31
+  blr
+  #_ REGISTER_OUT r3 0x00005678
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_9:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 16, 16, 31
+  blr
+  #_ REGISTER_OUT r3 0x00001234
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_9_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  rlwinm r3, r4, 16, 16, 31
+  blr
+  #_ REGISTER_OUT r3 0x00001234
+  #_ REGISTER_OUT r4 0x12345678
+
+test_extrwi_cr_1:
+  #_ REGISTER_IN r5 0x30
+  extrwi. r7, r5, 4, 25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0x30
+  #_ REGISTER_OUT r7 0x06
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extrwi_cr_1_constant:
+  li r5, 0x30
+  extrwi. r7, r5, 4, 25
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0x30
+  #_ REGISTER_OUT r7 0x06
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extrwi_cr_2:
+  #_ REGISTER_IN r5 0xFFFFFFFF01234567
+  extrwi. r7, r5, 16, 10
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF01234567
+  #_ REGISTER_OUT r7 0x0000000000008D15
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extrwi_cr_2_constant:
+  li r5, -1
+  sldi r5, r5, 32
+  oris r5, r5, 0x0123
+  ori r5, r5, 0x4567
+  extrwi. r7, r5, 16, 10
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF01234567
+  #_ REGISTER_OUT r7 0x0000000000008D15
+  #_ REGISTER_OUT r12 0x40000000
+
+test_extrwi_cr_3:
+  #_ REGISTER_IN r5 0xFFFFFFFF00000000
+  extrwi. r7, r5, 16, 10
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF00000000
+  #_ REGISTER_OUT r7 0x0000000000000000
+  #_ REGISTER_OUT r12 0x20000000
+
+test_extrwi_cr_3_constant:
+  li r5, -1
+  sldi r5, r5, 32
+  extrwi. r7, r5, 16, 10
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF00000000
+  #_ REGISTER_OUT r7 0x0000000000000000
+  #_ REGISTER_OUT r12 0x20000000

src/xenia/cpu/frontend/testing/instr_rlwnm.s

@@ -0,0 +1,193 @@
+test_rlwnm_1:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 24
+  rlwnm r3, r4, r5, 8, 15
+  blr
+  #_ REGISTER_OUT r3 0x00120000
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 24
+
+test_rlwnm_1_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  li r5, 24
+  rlwnm r3, r4, r5, 8, 15
+  blr
+  #_ REGISTER_OUT r3 0x00120000
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 24
+
+test_rlwnm_2:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 4
+  rlwnm r3, r4, r5, 0, 27
+  blr
+  #_ REGISTER_OUT r3 0x23456780
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 4
+
+test_rlwnm_2_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  li r5, 4
+  rlwnm r3, r4, r5, 0, 27
+  blr
+  #_ REGISTER_OUT r3 0x23456780
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 4
+
+test_rlwnm_3:
+  #_ REGISTER_IN r4 0x90003000
+  #_ REGISTER_IN r5 2
+  rlwnm r3, r4, r5, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0x4000C000
+  #_ REGISTER_OUT r4 0x90003000
+  #_ REGISTER_OUT r5 2
+
+test_rlwnm_3_constant:
+  lis r4, 0x9000
+  ori r4, r4, 0x3000
+  clrldi r4, r4, 32
+  li r5, 2
+  rlwnm r3, r4, r5, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0x4000C000
+  #_ REGISTER_OUT r4 0x90003000
+  #_ REGISTER_OUT r5 2
+
+test_rlwnm_4:
+  #_ REGISTER_IN r4 0xB0043000
+  #_ REGISTER_IN r5 2
+  rlwnm. r3, r4, r5, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0xC010C000
+  #_ REGISTER_OUT r4 0xB0043000
+  #_ REGISTER_OUT r5 2
+  # CRF = 0x8
+
+test_rlwnm_4_constant:
+  lis r4, 0xB004
+  ori r4, r4, 0x3000
+  clrldi r4, r4, 32
+  li r5, 2
+  rlwnm. r3, r4, r5, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0xC010C000
+  #_ REGISTER_OUT r4 0xB0043000
+  #_ REGISTER_OUT r5 2
+  # CRF = 0x8
+
+test_rlwnm_5:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 0
+  rlwnm r3, r4, r5, 5, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0x02345678
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 0
+
+test_rlwnm_5_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  li r5, 0
+  rlwnm r3, r4, r5, 5, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0x02345678
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 0
+
+test_rlwnm_6:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 0
+  rlwnm r3, r4, r5, 0, 31
+  blr
+  #_ REGISTER_OUT r3 0x12345678
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 0
+
+test_rlwnm_6_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  li r5, 0
+  rlwnm r3, r4, r5, 0, 31
+  blr
+  #_ REGISTER_OUT r3 0x12345678
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 0
+
+test_rlwnm_7:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 0
+  rlwnm r3, r4, r5, 0, 16
+  blr
+  #_ REGISTER_OUT r3 0x12340000
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 0
+
+test_rlwnm_7_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  li r5, 0
+  rlwnm r3, r4, r5, 0, 16
+  blr
+  #_ REGISTER_OUT r3 0x12340000
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 0
+
+test_rlwnm_8:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 0
+  rlwnm r3, r4, r5, 16, 31
+  blr
+  #_ REGISTER_OUT r3 0x00005678
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 0
+
+test_rlwnm_8_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  li r5, 0
+  rlwnm r3, r4, r5, 16, 31
+  blr
+  #_ REGISTER_OUT r3 0x00005678
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 0
+
+test_rlwnm_9:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 16
+  rlwnm r3, r4, r5, 16, 31
+  blr
+  #_ REGISTER_OUT r3 0x00001234
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 16
+
+test_rlwnm_9_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  li r5, 16
+  rlwnm r3, r4, r5, 16, 31
+  blr
+  #_ REGISTER_OUT r3 0x00001234
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 16
+
+test_rlwnm_10:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 32
+  rlwnm r3, r4, r5, 0, 31
+  blr
+  #_ REGISTER_OUT r3 0x12345678
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 32
+
+test_rlwnm_10_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  li r5, 32
+  rlwnm r3, r4, r5, 0, 31
+  blr
+  #_ REGISTER_OUT r3 0x12345678
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 32

src/xenia/cpu/frontend/testing/instr_sld.s

@@ -0,0 +1,125 @@
+test_sld_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_sld_1_constant:
+  li r4, 1
+  li r5, 0
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_sld_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+
+test_sld_2_constant:
+  li r4, -1
+  li r5, 0
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+
+test_sld_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_sld_3_constant:
+  li r4, -1
+  li r5, 1
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_sld_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 62
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xc000000000000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 62
+
+test_sld_4_constant:
+  li r4, -1
+  li r5, 62
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xc000000000000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 62
+
+test_sld_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 63
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 63
+
+test_sld_5_constant:
+  li r4, -1
+  li r5, 63
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 63
+
+test_sld_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 64
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 64
+
+test_sld_6_constant:
+  li r4, -1
+  li r5, 64
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 64
+
+test_sld_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 100
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 100
+
+test_sld_7_constant:
+  li r4, -1
+  li r5, 100
+  sld r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 100

src/xenia/cpu/frontend/testing/instr_slw.s

@@ -0,0 +1,161 @@
+test_slw_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_slw_1_constant:
+  li r4, 1
+  li r5, 0
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_slw_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+
+test_slw_2_constant:
+  li r4, -1
+  li r5, 0
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+
+test_slw_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_slw_3_constant:
+  li r4, -1
+  li r5, 1
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_slw_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 63
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 63
+
+test_slw_4_constant:
+  li r4, -1
+  li r5, 63
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 63
+
+test_slw_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 64
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 64
+
+test_slw_5_constant:
+  li r4, -1
+  li r5, 64
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 64
+
+test_slw_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 100
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 100
+
+test_slw_6_constant:
+  li r4, -1
+  li r5, 100
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 100
+
+test_slw_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 30
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000c0000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 30
+
+test_slw_7_constant:
+  li r4, -1
+  li r5, 30
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000c0000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 30
+
+test_slw_8:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 31
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000080000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 31
+
+test_slw_8_constant:
+  li r4, -1
+  li r5, 31
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000080000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 31
+
+test_slw_9:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 32
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 32
+
+test_slw_9_constant:
+  li r4, -1
+  li r5, 32
+  slw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 32

src/xenia/cpu/frontend/testing/instr_srad.s

@@ -0,0 +1,153 @@
+test_srad_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+
+test_srad_1_constant:
+  li r4, 1
+  li r5, 0
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+
+test_srad_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+
+test_srad_2_constant:
+  li r4, -1
+  li r5, 0
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+
+test_srad_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+
+test_srad_3_constant:
+  li r4, -1
+  li r5, 1
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+
+test_srad_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 62
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 62
+  #_ REGISTER_OUT r6 1
+
+test_srad_4_constant:
+  li r4, -1
+  li r5, 62
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 62
+  #_ REGISTER_OUT r6 1
+
+test_srad_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 63
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 63
+  #_ REGISTER_OUT r6 1
+
+test_srad_5_constant:
+  li r4, -1
+  li r5, 63
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 63
+  #_ REGISTER_OUT r6 1
+
+test_srad_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 64
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 64
+  #_ REGISTER_OUT r6 1
+
+test_srad_6_constant:
+  li r4, -1
+  li r5, 64
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 64
+  #_ REGISTER_OUT r6 1
+
+test_srad_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 100
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 100
+  #_ REGISTER_OUT r6 1
+
+test_srad_7_constant:
+  li r4, -1
+  li r5, 100
+  srad r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 100
+  #_ REGISTER_OUT r6 1

src/xenia/cpu/frontend/testing/instr_sradi.s

@@ -0,0 +1,89 @@
+test_sradi_1:
+  #_ REGISTER_IN r4 1
+  sradi r3, r4, 0
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 0
+
+test_sradi_1_constant:
+  li r4, 1
+  sradi r3, r4, 0
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 0
+
+test_sradi_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  sradi r3, r4, 0
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 0
+
+test_sradi_2_constant:
+  li r4, -1
+  sradi r3, r4, 0
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 0
+
+test_sradi_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  sradi r3, r4, 1
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_sradi_3_constant:
+  li r4, -1
+  sradi r3, r4, 1
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_sradi_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  sradi r3, r4, 62
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_sradi_4_constant:
+  li r4, -1
+  sradi r3, r4, 62
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_sradi_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  sradi r3, r4, 63
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_sradi_5_constant:
+  li r4, -1
+  sradi r3, r4, 63
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1

src/xenia/cpu/frontend/testing/instr_sraw.s

@@ -0,0 +1,197 @@
+test_sraw_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+
+test_sraw_1_constant:
+  li r4, 1
+  li r5, 0
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+
+test_sraw_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+
+test_sraw_2_constant:
+  li r4, -1
+  li r5, 0
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+
+test_sraw_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+
+test_sraw_3_constant:
+  li r4, -1
+  li r5, 1
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+
+test_sraw_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 63
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 63
+  #_ REGISTER_OUT r6 1
+
+test_sraw_4_constant:
+  li r4, -1
+  li r5, 63
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 63
+  #_ REGISTER_OUT r6 1
+
+test_sraw_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 64
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 64
+  #_ REGISTER_OUT r6 0
+
+test_sraw_5_constant:
+  li r4, -1
+  li r5, 64
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 64
+  #_ REGISTER_OUT r6 0
+
+test_sraw_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 100
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 100
+  #_ REGISTER_OUT r6 1
+
+test_sraw_6_constant:
+  li r4, -1
+  li r5, 100
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 100
+  #_ REGISTER_OUT r6 1
+
+test_sraw_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 30
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 30
+  #_ REGISTER_OUT r6 1
+
+test_sraw_7_constant:
+  li r4, -1
+  li r5, 30
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 30
+  #_ REGISTER_OUT r6 1
+
+test_sraw_8:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 31
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 31
+  #_ REGISTER_OUT r6 1
+
+test_sraw_8_constant:
+  li r4, -1
+  li r5, 31
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 31
+  #_ REGISTER_OUT r6 1
+
+test_sraw_9:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 32
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 32
+  #_ REGISTER_OUT r6 1
+
+test_sraw_9_constant:
+  li r4, -1
+  li r5, 32
+  sraw r3, r4, r5
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 32
+  #_ REGISTER_OUT r6 1

src/xenia/cpu/frontend/testing/instr_srawi.s

@@ -0,0 +1,89 @@
+test_srawi_1:
+  #_ REGISTER_IN r4 1
+  srawi r3, r4, 0
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 0
+
+test_srawi_1_constant:
+  li r4, 1
+  srawi r3, r4, 0
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r6 0
+
+test_srawi_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  srawi r3, r4, 0
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 0
+
+test_srawi_2_constant:
+  li r4, -1
+  srawi r3, r4, 0
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 0
+
+test_srawi_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  srawi r3, r4, 1
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_srawi_3_constant:
+  li r4, -1
+  srawi r3, r4, 1
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_srawi_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  srawi r3, r4, 30
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_srawi_4_constant:
+  li r4, -1
+  srawi r3, r4, 30
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_srawi_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  srawi r3, r4, 31
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+
+test_srawi_5_constant:
+  li r4, -1
+  srawi r3, r4, 31
+  adde r6, r0, r0
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1

src/xenia/cpu/frontend/testing/instr_srd.s

@@ -0,0 +1,125 @@
+test_srd_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_srd_1_constant:
+  li r4, 1
+  li r5, 0
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_srd_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+
+test_srd_2_constant:
+  li r4, -1
+  li r5, 0
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+
+test_srd_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_srd_3_constant:
+  li r4, -1
+  li r5, 1
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_srd_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 62
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000003
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 62
+
+test_srd_4_constant:
+  li r4, -1
+  li r5, 62
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000003
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 62
+
+test_srd_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 63
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 63
+
+test_srd_5_constant:
+  li r4, -1
+  li r5, 63
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 63
+
+test_srd_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 64
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 64
+
+test_srd_6_constant:
+  li r4, -1
+  li r5, 64
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 64
+
+test_srd_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 100
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 100
+
+test_srd_7_constant:
+  li r4, -1
+  li r5, 100
+  srd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 100

src/xenia/cpu/frontend/testing/instr_srw.s

@@ -0,0 +1,161 @@
+test_srw_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_srw_1_constant:
+  li r4, 1
+  li r5, 0
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0
+
+test_srw_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+
+test_srw_2_constant:
+  li r4, -1
+  li r5, 0
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+
+test_srw_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_srw_3_constant:
+  li r4, -1
+  li r5, 1
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_srw_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 63
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 63
+
+test_srw_4_constant:
+  li r4, -1
+  li r5, 63
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 63
+
+test_srw_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 64
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 64
+
+test_srw_5_constant:
+  li r4, -1
+  li r5, 64
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 64
+
+test_srw_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 100
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 100
+
+test_srw_6_constant:
+  li r4, -1
+  li r5, 100
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 100
+
+test_srw_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 30
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000003
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 30
+
+test_srw_7_constant:
+  li r4, -1
+  li r5, 30
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000003
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 30
+
+test_srw_8:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 31
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 31
+
+test_srw_8_constant:
+  li r4, -1
+  li r5, 31
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 31
+
+test_srw_9:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 32
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 32
+
+test_srw_9_constant:
+  li r4, -1
+  li r5, 32
+  srw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 32

src/xenia/cpu/frontend/testing/instr_stvew.s

@@ -0,0 +1,79 @@
+test_stvew_1:
+  #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
+  #_ REGISTER_IN r4 0x1050
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  stvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x1050
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ MEMORY_OUT 00001050 00010203 CCCCCCCC CCCCCCCC CCCCCCCC
+
+test_stvew_1_constant:
+  #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
+  li r4, 0x1050
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  stvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x1050
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ MEMORY_OUT 00001050 00010203 CCCCCCCC CCCCCCCC CCCCCCCC
+
+test_stvew_2:
+  #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
+  #_ REGISTER_IN r4 0x1054
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  stvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x1054
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ MEMORY_OUT 00001050 CCCCCCCC 04050607 CCCCCCCC CCCCCCCC
+
+test_stvew_2_constant:
+  #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
+  li r4, 0x1054
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  stvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x1054
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ MEMORY_OUT 00001050 CCCCCCCC 04050607 CCCCCCCC CCCCCCCC
+
+test_stvew_3:
+  #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
+  #_ REGISTER_IN r4 0x1058
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  stvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x1058
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC 08090A0B CCCCCCCC
+
+test_stvew_3_constant:
+  #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
+  li r4, 0x1058
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  stvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x1058
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC 08090A0B CCCCCCCC
+
+test_stvew_4:
+  #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
+  #_ REGISTER_IN r4 0x105C
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  stvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x105C
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC CCCCCCCC 0C0D0E0F
+
+test_stvew_4_constant:
+  #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
+  li r4, 0x105C
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  stvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x105C
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC CCCCCCCC 0C0D0E0F

src/xenia/cpu/frontend/testing/instr_stvl.s

@@ -0,0 +1,39 @@
+test_stvl_1:
+  #_ MEMORY_IN 00001040 00000000 00000000 00000000 3F800000
+  #_ REGISTER_IN r4 0x1040
+  #_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
+  stvlx v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1040
+  #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
+  #_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F
+
+test_stvl_1_constant:
+  #_ MEMORY_IN 00001040 00000000 00000000 00000000 3F800000
+  li r4, 0x1040
+  #_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
+  stvlx v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1040
+  #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
+  #_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F
+
+test_stvl_2:
+  #_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F
+  #_ REGISTER_IN r4 0x1044
+  #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  stvlx v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1044
+  #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  #_ MEMORY_OUT 00001040 00010203 F0F1F2F3 F4F5F6F7 F8F9FAFB
+
+test_stvl_2_constant:
+  #_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F
+  li r4, 0x1044
+  #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  stvlx v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1044
+  #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  #_ MEMORY_OUT 00001040 00010203 F0F1F2F3 F4F5F6F7 F8F9FAFB

src/xenia/cpu/frontend/testing/instr_stvr.s

@@ -0,0 +1,47 @@
+test_stvr_1:
+  #_ MEMORY_IN 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F
+  #_ MEMORY_IN 00001050 00000000 00000000 00000000 00000000
+  #_ REGISTER_IN r4 0x1040
+  #_ REGISTER_IN r5 0x10
+  #_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
+  stvrx v3, r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x1040
+  #_ REGISTER_OUT r5 0x10
+  #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
+  #_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F
+  #_ MEMORY_OUT 00001050 00000000 00000000 00000000 00000000
+
+test_stvr_1_constant:
+  #_ MEMORY_IN 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F
+  #_ MEMORY_IN 00001050 00000000 00000000 00000000 00000000
+  li r4, 0x1040
+  li r5, 0x10
+  #_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
+  stvrx v3, r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x1040
+  #_ REGISTER_OUT r5 0x10
+  #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
+  #_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F
+  #_ MEMORY_OUT 00001050 00000000 00000000 00000000 00000000
+
+test_stvr_2:
+  #_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F
+  #_ REGISTER_IN r4 0x1044
+  #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  stvrx v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1044
+  #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  #_ MEMORY_OUT 00001040 FCFDFEFF 04050607 08090A0B 0C0D0E0F
+
+test_stvr_2_constant:
+  #_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F
+  li r4, 0x1044
+  #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  stvrx v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1044
+  #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  #_ MEMORY_OUT 00001040 FCFDFEFF 04050607 08090A0B 0C0D0E0F

src/xenia/cpu/frontend/testing/instr_subf.s

@@ -0,0 +1,91 @@
+test_subf_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  #_ REGISTER_IN r11 0x00000000000103C0
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r11 0x00000000000103C0
+  #_ REGISTER_OUT r3 0x1
+
+test_subf_1_constant:
+  lis r10, 1
+  ori r10, r10, 0x03BF
+  lis r11, 1
+  ori r11, r11, 0x03C0
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r11 0x00000000000103C0
+  #_ REGISTER_OUT r3 0x1
+
+test_subf_2:
+  #_ REGISTER_IN r10 0
+  #_ REGISTER_IN r11 0
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 0
+
+test_subf_2_constant:
+  li r10, 0
+  li r11, 0
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 0
+
+test_subf_3:
+  #_ REGISTER_IN r10 1
+  #_ REGISTER_IN r11 0
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 -1
+
+test_subf_3_constant:
+  li r10, 1
+  li r11, 0
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 -1
+
+test_subf_4:
+  #_ REGISTER_IN r10 0
+  #_ REGISTER_IN r11 1
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 1
+  #_ REGISTER_OUT r3 1
+
+test_subf_4_constant:
+  li r10, 0
+  li r11, 1
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 1
+  #_ REGISTER_OUT r3 1
+
+test_subf_5:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0x0
+
+test_subf_5_constant:
+  li r10, -1
+  li r11, -1
+  subf r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0x0

src/xenia/cpu/frontend/testing/instr_subfc.s

@@ -0,0 +1,111 @@
+test_subfc_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  #_ REGISTER_IN r11 0x00000000000103C0
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r11 0x00000000000103C0
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+
+test_subfc_1_constant:
+  lis r10, 1
+  ori r10, r10, 0x03BF
+  lis r11, 1
+  ori r11, r11, 0x03C0
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r11 0x00000000000103C0
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+
+test_subfc_2:
+  #_ REGISTER_IN r10 0
+  #_ REGISTER_IN r11 0
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfc_2_constant:
+  li r10, 0
+  li r11, 0
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfc_3:
+  #_ REGISTER_IN r10 1
+  #_ REGISTER_IN r11 0
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_subfc_3_constant:
+  li r10, 1
+  li r11, 0
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_subfc_4:
+  #_ REGISTER_IN r10 0
+  #_ REGISTER_IN r11 1
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 1
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+
+test_subfc_4_constant:
+  li r10, 0
+  li r11, 1
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 1
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+
+test_subfc_5:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfc_5_constant:
+  li r10, -1
+  li r11, -1
+  subfc r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1

src/xenia/cpu/frontend/testing/instr_subfe.s

@@ -0,0 +1,111 @@
+test_subfe_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  #_ REGISTER_IN r11 0x00000000000103C0
+  subfe r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r11 0x00000000000103C0
+  #_ REGISTER_OUT r3 0x0
+  #_ REGISTER_OUT r4 1
+
+test_subfe_1_constant:
+  lis r10, 1
+  ori r10, r10, 0x03BF
+  lis r11, 1
+  ori r11, r11, 0x03C0
+  subfe r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r11 0x00000000000103C0
+  #_ REGISTER_OUT r3 0x0
+  #_ REGISTER_OUT r4 1
+
+test_subfe_2:
+  #_ REGISTER_IN r10 0
+  #_ REGISTER_IN r11 0
+  subfe r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0
+
+test_subfe_2_constant:
+  li r10, 0
+  li r11, 0
+  subfe r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0
+
+test_subfe_3:
+  #_ REGISTER_IN r10 1
+  #_ REGISTER_IN r11 0
+  subfe r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0
+
+test_subfe_3_constant:
+  li r10, 1
+  li r11, 0
+  subfe r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0
+
+test_subfe_4:
+  #_ REGISTER_IN r10 0
+  #_ REGISTER_IN r11 1
+  subfe r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 1
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfe_4_constant:
+  li r10, 0
+  li r11, 1
+  subfe r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 1
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfe_5:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
+  subfe r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0
+
+test_subfe_5_constant:
+  li r10, -1
+  li r11, -1
+  subfe r3, r10, r11
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0

src/xenia/cpu/frontend/testing/instr_subfic.s

@@ -0,0 +1,109 @@
+test_subfic_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  subfic r3, r10, 0x3C0
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xffffffffffff0001
+  #_ REGISTER_OUT r4 0
+
+test_subfic_1_constant:
+  lis r10, 1
+  ori r10, r10, 0x03BF
+  subfic r3, r10, 0x3C0
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xffffffffffff0001
+  #_ REGISTER_OUT r4 0
+
+test_subfic_2:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  subfic r3, r10, -234
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefb57
+  #_ REGISTER_OUT r4 1
+
+test_subfic_2_constant:
+  lis r10, 1
+  ori r10, r10, 0x03BF
+  subfic r3, r10, -234
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefb57
+  #_ REGISTER_OUT r4 1
+
+test_subfic_3:
+  #_ REGISTER_IN r10 0
+  subfic r3, r10, 0
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfic_3_constant:
+  li r10, 0
+  subfic r3, r10, 0
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfic_4:
+  #_ REGISTER_IN r10 1
+  subfic r3, r10, 0
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_subfic_4_constant:
+  li r10, 1
+  subfic r3, r10, 0
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_subfic_5:
+  #_ REGISTER_IN r10 0
+  subfic r3, r10, 1
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+
+test_subfic_5_constant:
+  li r10, 0
+  subfic r3, r10, 1
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 1
+
+test_subfic_6:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  subfic r3, r10, -1
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfic_6_constant:
+  li r10, -1
+  subfic r3, r10, -1
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1

src/xenia/cpu/frontend/testing/instr_subfme.s

@@ -0,0 +1,185 @@
+test_subfme_one_ca_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefc40
+  #_ REGISTER_OUT r4 1
+
+test_subfme_one_ca_1_constant:
+  lis r10, 1
+  ori r10, r10, 0x03BF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefc40
+  #_ REGISTER_OUT r4 1
+
+test_subfme_one_ca_2:
+  #_ REGISTER_IN r10 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 1
+
+test_subfme_one_ca_2_constant:
+  li r10, 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 1
+
+test_subfme_one_ca_3:
+  #_ REGISTER_IN r10 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 1
+
+test_subfme_one_ca_3_constant:
+  li r10, 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 1
+
+test_subfme_one_ca_4:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfme_one_ca_4_constant:
+  li r10, -1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfme_zero_ca_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefc3f
+  #_ REGISTER_OUT r4 1
+
+test_subfme_zero_ca_1_constant:
+  lis r10, 1
+  ori r10, r10, 0x03BF
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefc3f
+  #_ REGISTER_OUT r4 1
+
+test_subfme_zero_ca_2:
+  #_ REGISTER_IN r10 0
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 1
+
+test_subfme_zero_ca_2_constant:
+  li r10, 0
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 1
+
+test_subfme_zero_ca_3:
+  #_ REGISTER_IN r10 1
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 0xfffffffffffffffd
+  #_ REGISTER_OUT r4 1
+
+test_subfme_zero_ca_3_constant:
+  li r10, 1
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 0xfffffffffffffffd
+  #_ REGISTER_OUT r4 1
+
+test_subfme_zero_ca_4:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0
+
+test_subfme_zero_ca_4_constant:
+  li r10, -1
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfme r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0

src/xenia/cpu/frontend/testing/instr_subfze.s

@@ -0,0 +1,185 @@
+test_subfze_one_ca_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefc41
+  #_ REGISTER_OUT r4 0
+
+test_subfze_one_ca_1_constant:
+  lis r10, 1
+  ori r10, r10, 0x03BF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefc41
+  #_ REGISTER_OUT r4 0
+
+test_subfze_one_ca_2:
+  #_ REGISTER_IN r10 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfze_one_ca_2_constant:
+  li r10, 0
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+
+test_subfze_one_ca_3:
+  #_ REGISTER_IN r10 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_subfze_one_ca_3_constant:
+  li r10, 1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_subfze_one_ca_4:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0x1
+  #_ REGISTER_OUT r4 0
+
+test_subfze_one_ca_4_constant:
+  li r10, -1
+  xor r3, r3, r3
+  not r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0x1
+  #_ REGISTER_OUT r4 0
+
+test_subfze_zero_ca_1:
+  #_ REGISTER_IN r10 0x00000000000103BF
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefc40
+  #_ REGISTER_OUT r4 0
+
+test_subfze_zero_ca_1_constant:
+  lis r10, 1
+  ori r10, r10, 0x03BF
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0x00000000000103BF
+  #_ REGISTER_OUT r3 0xfffffffffffefc40
+  #_ REGISTER_OUT r4 0
+
+test_subfze_zero_ca_2:
+  #_ REGISTER_IN r10 0
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0
+
+test_subfze_zero_ca_2_constant:
+  li r10, 0
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0
+
+test_subfze_zero_ca_3:
+  #_ REGISTER_IN r10 1
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0
+
+test_subfze_zero_ca_3_constant:
+  li r10, 1
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0
+
+test_subfze_zero_ca_4:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+
+test_subfze_zero_ca_4_constant:
+  li r10, -1
+  xor r3, r3, r3
+  addic r3, r3, 1
+  subfze r3, r10
+  adde r4, r0, r0
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0

src/xenia/cpu/frontend/testing/instr_td.s

@@ -0,0 +1,511 @@
+test_tdlt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  tdlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdlt_1_constant:
+  li r3, 24
+  li r4, 16
+  tdlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdlt_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdlt_2_constant:
+  li r3, 24
+  li r4, 0
+  tdlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdle_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  tdle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdle_1_constant:
+  li r3, 24
+  li r4, 16
+  tdle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdle_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdle_2_constant:
+  li r3, 24
+  li r4, 0
+  tdle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdeq_1:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 24
+  tdeq r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 24
+
+test_tdeq_1_constant:
+  li r3, 0
+  li r4, 24
+  tdeq r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 24
+
+test_tdeq_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdeq r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdeq_2_constant:
+  li r3, 24
+  li r4, 0
+  tdeq r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdge_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  tdge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdge_1_constant:
+  li r3, 24
+  li r4, 48
+  tdge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdge_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  tdge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdge_2_constant:
+  li r3, 0
+  li r4, 48
+  tdge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdge_3:
+  #_ REGISTER_IN r3 -1
+  #_ REGISTER_IN r4 0
+  tdge r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_tdge_3_constant:
+  li r3, -1
+  li r4, 0
+  tdge r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_tdgt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  tdgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdgt_1_constant:
+  li r3, 24
+  li r4, 48
+  tdgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdgt_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  tdgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdgt_2_constant:
+  li r3, 0
+  li r4, 48
+  tdgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdgt_3:
+  #_ REGISTER_IN r3 -1
+  #_ REGISTER_IN r4 0
+  tdgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_tdgt_3_constant:
+  li r3, -1
+  li r4, 0
+  tdgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_tdnl_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  tdnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdnl_1_constant:
+  li r3, 24
+  li r4, 48
+  tdnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdnl_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  tdnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdnl_2_constant:
+  li r3, 0
+  li r4, 48
+  tdnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdnl_3:
+  #_ REGISTER_IN r3 -1
+  #_ REGISTER_IN r4 0
+  tdnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_tdnl_3_constant:
+  li r3, -1
+  li r4, 0
+  tdnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_tdne_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 24
+  tdne r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 24
+
+test_tdne_1_constant:
+  li r3, 24
+  li r4, 24
+  tdne r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 24
+
+test_tdne_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 0
+  tdne r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+
+test_tdne_2_constant:
+  li r3, 0
+  li r4, 0
+  tdne r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+
+test_tdng_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  tdng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdng_1_constant:
+  li r3, 24
+  li r4, 16
+  tdng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdng_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdng_2_constant:
+  li r3, 24
+  li r4, 0
+  tdng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdng_3:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 -1
+  tdng r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 -1
+
+test_tdng_3_constant:
+  li r3, 0
+  li r4, -1
+  tdng r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 -1
+
+test_tdllt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  tdllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdllt_1_constant:
+  li r3, 24
+  li r4, 16
+  tdllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdllt_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdllt_2_constant:
+  li r3, 24
+  li r4, 0
+  tdllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdlle_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  tdlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdlle_1_constant:
+  li r3, 24
+  li r4, 16
+  tdlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdlle_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdlle_2_constant:
+  li r3, 24
+  li r4, 0
+  tdlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdlge_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  tdlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdlge_1_constant:
+  li r3, 24
+  li r4, 48
+  tdlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdlge_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  tdlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdlge_2_constant:
+  li r3, 0
+  li r4, 48
+  tdlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdlgt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  tdlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdlgt_1_constant:
+  li r3, 24
+  li r4, 48
+  tdlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdlgt_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  tdlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdlgt_2_constant:
+  li r3, 0
+  li r4, 48
+  tdlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdlnl_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  tdlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdlnl_1_constant:
+  li r3, 24
+  li r4, 48
+  tdlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdlnl_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  tdlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdlnl_2_constant:
+  li r3, 0
+  li r4, 48
+  tdlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdlng_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  tdlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdlng_1_constant:
+  li r3, 24
+  li r4, 16
+  tdlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdlng_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdlng_2_constant:
+  li r3, 24
+  li r4, 0
+  tdlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0

src/xenia/cpu/frontend/testing/instr_tdi.s

@@ -0,0 +1,383 @@
+test_tdlti_1:
+  #_ REGISTER_IN r3 24
+  tdlti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlti_1_constant:
+  li r3, 24
+  tdlti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlti_2:
+  #_ REGISTER_IN r3 24
+  tdlti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlti_2_constant:
+  li r3, 24
+  tdlti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlei_1:
+  #_ REGISTER_IN r3 24
+  tdlei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlei_1_constant:
+  li r3, 24
+  tdlei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlei_2:
+  #_ REGISTER_IN r3 24
+  tdlei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlei_2_constant:
+  li r3, 24
+  tdlei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdeqi_1:
+  #_ REGISTER_IN r3 0
+  tdeqi r3, 24
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdeqi_1_constant:
+  li r3, 0
+  tdeqi r3, 24
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdeqi_2:
+  #_ REGISTER_IN r3 24
+  tdeqi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdeqi_2_constant:
+  li r3, 24
+  tdeqi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdgei_1:
+  #_ REGISTER_IN r3 24
+  tdgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdgei_1_constant:
+  li r3, 24
+  tdgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdgei_2:
+  #_ REGISTER_IN r3 0
+  tdgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdgei_2_constant:
+  li r3, 0
+  tdgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdgei_3:
+  #_ REGISTER_IN r3 -1
+  tdgei r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_tdgei_3_constant:
+  li r3, -1
+  tdgei r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_tdgti_1:
+  #_ REGISTER_IN r3 24
+  tdgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdgti_1_constant:
+  li r3, 24
+  tdgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdgti_2:
+  #_ REGISTER_IN r3 0
+  tdgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdgti_2_constant:
+  li r3, 0
+  tdgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdgti_3:
+  #_ REGISTER_IN r3 -1
+  tdgti r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_tdgti_3_constant:
+  li r3, -1
+  tdgti r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_tdnli_1:
+  #_ REGISTER_IN r3 24
+  tdnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdnli_1_constant:
+  li r3, 24
+  tdnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdnli_2:
+  #_ REGISTER_IN r3 0
+  tdnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdnli_2_constant:
+  li r3, 0
+  tdnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdnli_3:
+  #_ REGISTER_IN r3 -1
+  tdnli r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_tdnli_3_constant:
+  li r3, -1
+  tdnli r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_tdnei_1:
+  #_ REGISTER_IN r3 24
+  tdnei r3, 24
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdnei_1_constant:
+  li r3, 24
+  tdnei r3, 24
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdnei_2:
+  #_ REGISTER_IN r3 0
+  tdnei r3, 0
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdnei_2_constant:
+  li r3, 0
+  tdnei r3, 0
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdngi_1:
+  #_ REGISTER_IN r3 24
+  tdngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdngi_1_constant:
+  li r3, 24
+  tdngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdngi_2:
+  #_ REGISTER_IN r3 24
+  tdngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdngi_2_constant:
+  li r3, 24
+  tdngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdngi_3:
+  #_ REGISTER_IN r3 0
+  tdngi r3, -1
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdngi_3_constant:
+  li r3, 0
+  tdngi r3, -1
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdllti_1:
+  #_ REGISTER_IN r3 24
+  tdllti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllti_1_constant:
+  li r3, 24
+  tdllti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllti_2:
+  #_ REGISTER_IN r3 24
+  tdllti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllti_2_constant:
+  li r3, 24
+  tdllti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllei_1:
+  #_ REGISTER_IN r3 24
+  tdllei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllei_1_constant:
+  li r3, 24
+  tdllei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllei_2:
+  #_ REGISTER_IN r3 24
+  tdllei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllei_2_constant:
+  li r3, 24
+  tdllei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlgei_1:
+  #_ REGISTER_IN r3 24
+  tdlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlgei_1_constant:
+  li r3, 24
+  tdlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlgei_2:
+  #_ REGISTER_IN r3 0
+  tdlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdlgei_2_constant:
+  li r3, 0
+  tdlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdlgti_1:
+  #_ REGISTER_IN r3 24
+  tdlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlgti_1_constant:
+  li r3, 24
+  tdlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlgti_2:
+  #_ REGISTER_IN r3 0
+  tdlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdlgti_2_constant:
+  li r3, 0
+  tdlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdlnli_1:
+  #_ REGISTER_IN r3 24
+  tdlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlnli_1_constant:
+  li r3, 24
+  tdlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlnli_2:
+  #_ REGISTER_IN r3 0
+  tdlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdlnli_2_constant:
+  li r3, 0
+  tdlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdlngi_1:
+  #_ REGISTER_IN r3 24
+  tdlngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlngi_1_constant:
+  li r3, 24
+  tdlngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlngi_2:
+  #_ REGISTER_IN r3 24
+  tdlngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlngi_2_constant:
+  li r3, 24
+  tdlngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24

src/xenia/cpu/frontend/testing/instr_tw.s

@@ -0,0 +1,511 @@
+test_twlt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  twlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twlt_1_constant:
+  li r3, 24
+  li r4, 16
+  twlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twlt_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  twlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twlt_2_constant:
+  li r3, 24
+  li r4, 0
+  twlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twle_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  twle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twle_1_constant:
+  li r3, 24
+  li r4, 16
+  twle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twle_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  twle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twle_2_constant:
+  li r3, 24
+  li r4, 0
+  twle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tweq_1:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 24
+  tweq r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 24
+
+test_tweq_1_constant:
+  li r3, 0
+  li r4, 24
+  tweq r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 24
+
+test_tweq_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tweq r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tweq_2_constant:
+  li r3, 24
+  li r4, 0
+  tweq r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twge_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  twge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twge_1_constant:
+  li r3, 24
+  li r4, 48
+  twge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twge_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  twge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twge_2_constant:
+  li r3, 0
+  li r4, 48
+  twge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twge_3:
+  #_ REGISTER_IN r3 -1
+  #_ REGISTER_IN r4 0
+  twge r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_twge_3_constant:
+  li r3, -1
+  li r4, 0
+  twge r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_twgt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  twgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twgt_1_constant:
+  li r3, 24
+  li r4, 48
+  twgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twgt_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  twgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twgt_2_constant:
+  li r3, 0
+  li r4, 48
+  twgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twgt_3:
+  #_ REGISTER_IN r3 -1
+  #_ REGISTER_IN r4 0
+  twgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_twgt_3_constant:
+  li r3, -1
+  li r4, 0
+  twgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_twnl_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  twnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twnl_1_constant:
+  li r3, 24
+  li r4, 48
+  twnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twnl_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  twnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twnl_2_constant:
+  li r3, 0
+  li r4, 48
+  twnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twnl_3:
+  #_ REGISTER_IN r3 -1
+  #_ REGISTER_IN r4 0
+  twnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_twnl_3_constant:
+  li r3, -1
+  li r4, 0
+  twnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_twne_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 24
+  twne r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 24
+
+test_twne_1_constant:
+  li r3, 24
+  li r4, 24
+  twne r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 24
+
+test_twne_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 0
+  twne r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+
+test_twne_2_constant:
+  li r3, 0
+  li r4, 0
+  twne r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+
+test_twng_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  twng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twng_1_constant:
+  li r3, 24
+  li r4, 16
+  twng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twng_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  twng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twng_2_constant:
+  li r3, 24
+  li r4, 0
+  twng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twng_3:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 -1
+  twng r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 -1
+
+test_twng_3_constant:
+  li r3, 0
+  li r4, -1
+  twng r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 -1
+
+test_twllt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  twllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twllt_1_constant:
+  li r3, 24
+  li r4, 16
+  twllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twllt_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  twllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twllt_2_constant:
+  li r3, 24
+  li r4, 0
+  twllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twlle_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  twlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twlle_1_constant:
+  li r3, 24
+  li r4, 16
+  twlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twlle_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  twlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twlle_2_constant:
+  li r3, 24
+  li r4, 0
+  twlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twlge_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  twlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twlge_1_constant:
+  li r3, 24
+  li r4, 48
+  twlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twlge_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  twlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twlge_2_constant:
+  li r3, 0
+  li r4, 48
+  twlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twlgt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  twlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twlgt_1_constant:
+  li r3, 24
+  li r4, 48
+  twlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twlgt_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  twlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twlgt_2_constant:
+  li r3, 0
+  li r4, 48
+  twlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twlnl_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  twlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twlnl_1_constant:
+  li r3, 24
+  li r4, 48
+  twlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twlnl_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  twlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twlnl_2_constant:
+  li r3, 0
+  li r4, 48
+  twlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twlng_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  twlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twlng_1_constant:
+  li r3, 24
+  li r4, 16
+  twlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twlng_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  twlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twlng_2_constant:
+  li r3, 24
+  li r4, 0
+  twlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0

src/xenia/cpu/frontend/testing/instr_twi.s

@@ -0,0 +1,383 @@
+test_twlti_1:
+  #_ REGISTER_IN r3 24
+  twlti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlti_1_constant:
+  li r3, 24
+  twlti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlti_2:
+  #_ REGISTER_IN r3 24
+  twlti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlti_2_constant:
+  li r3, 24
+  twlti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlei_1:
+  #_ REGISTER_IN r3 24
+  twlei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlei_1_constant:
+  li r3, 24
+  twlei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlei_2:
+  #_ REGISTER_IN r3 24
+  twlei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlei_2_constant:
+  li r3, 24
+  twlei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tweqi_1:
+  #_ REGISTER_IN r3 0
+  tweqi r3, 24
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tweqi_1_constant:
+  li r3, 0
+  tweqi r3, 24
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tweqi_2:
+  #_ REGISTER_IN r3 24
+  tweqi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tweqi_2_constant:
+  li r3, 24
+  tweqi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twgei_1:
+  #_ REGISTER_IN r3 24
+  twgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twgei_1_constant:
+  li r3, 24
+  twgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twgei_2:
+  #_ REGISTER_IN r3 0
+  twgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twgei_2_constant:
+  li r3, 0
+  twgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twgei_3:
+  #_ REGISTER_IN r3 -1
+  twgei r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_twgei_3_constant:
+  li r3, -1
+  twgei r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_twgti_1:
+  #_ REGISTER_IN r3 24
+  twgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twgti_1_constant:
+  li r3, 24
+  twgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twgti_2:
+  #_ REGISTER_IN r3 0
+  twgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twgti_2_constant:
+  li r3, 0
+  twgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twgti_3:
+  #_ REGISTER_IN r3 -1
+  twgti r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_twgti_3_constant:
+  li r3, -1
+  twgti r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_twnli_1:
+  #_ REGISTER_IN r3 24
+  twnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twnli_1_constant:
+  li r3, 24
+  twnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twnli_2:
+  #_ REGISTER_IN r3 0
+  twnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twnli_2_constant:
+  li r3, 0
+  twnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twnli_3:
+  #_ REGISTER_IN r3 -1
+  twnli r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_twnli_3_constant:
+  li r3, -1
+  twnli r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_twnei_1:
+  #_ REGISTER_IN r3 24
+  twnei r3, 24
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twnei_1_constant:
+  li r3, 24
+  twnei r3, 24
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twnei_2:
+  #_ REGISTER_IN r3 0
+  twnei r3, 0
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twnei_2_constant:
+  li r3, 0
+  twnei r3, 0
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twngi_1:
+  #_ REGISTER_IN r3 24
+  twngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twngi_1_constant:
+  li r3, 24
+  twngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twngi_2:
+  #_ REGISTER_IN r3 24
+  twngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twngi_2_constant:
+  li r3, 24
+  twngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twngi_3:
+  #_ REGISTER_IN r3 0
+  twngi r3, -1
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twngi_3_constant:
+  li r3, 0
+  twngi r3, -1
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twllti_1:
+  #_ REGISTER_IN r3 24
+  twllti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllti_1_constant:
+  li r3, 24
+  twllti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllti_2:
+  #_ REGISTER_IN r3 24
+  twllti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllti_2_constant:
+  li r3, 24
+  twllti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllei_1:
+  #_ REGISTER_IN r3 24
+  twllei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllei_1_constant:
+  li r3, 24
+  twllei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllei_2:
+  #_ REGISTER_IN r3 24
+  twllei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllei_2_constant:
+  li r3, 24
+  twllei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlgei_1:
+  #_ REGISTER_IN r3 24
+  twlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlgei_1_constant:
+  li r3, 24
+  twlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlgei_2:
+  #_ REGISTER_IN r3 0
+  twlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twlgei_2_constant:
+  li r3, 0
+  twlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twlgti_1:
+  #_ REGISTER_IN r3 24
+  twlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlgti_1_constant:
+  li r3, 24
+  twlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlgti_2:
+  #_ REGISTER_IN r3 0
+  twlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twlgti_2_constant:
+  li r3, 0
+  twlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twlnli_1:
+  #_ REGISTER_IN r3 24
+  twlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlnli_1_constant:
+  li r3, 24
+  twlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlnli_2:
+  #_ REGISTER_IN r3 0
+  twlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twlnli_2_constant:
+  li r3, 0
+  twlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twlngi_1:
+  #_ REGISTER_IN r3 24
+  twlngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlngi_1_constant:
+  li r3, 24
+  twlngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlngi_2:
+  #_ REGISTER_IN r3 24
+  twlngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlngi_2_constant:
+  li r3, 24
+  twlngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24

src/xenia/cpu/frontend/testing/instr_vaddshs.s

@@ -0,0 +1,7 @@
+test_vaddshs_1:
+  #_ REGISTER_IN v3 [7FFF8001, 7FFF8003, 7FFF8005, 80068007]
+  #_ REGISTER_IN v4 [00018001, 10000000, 42568124, 00000000]
+  vaddshs v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7fff8000, 7fff8003, 7fff8000, 80068007]
+  #_ REGISTER_OUT v4 [00018001, 10000000, 42568124, 00000000]

src/xenia/cpu/frontend/testing/instr_vadduhm.s

@@ -0,0 +1,7 @@
+test_vadduhm_1:
+  #_ REGISTER_IN v3 [7FFF8001, 7FFF8003, 7FFF8005, 80068007]
+  #_ REGISTER_IN v4 [00018001, 10000000, 42568124, 00000000]
+  vadduhm v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000002, 8fff8003, c2550129, 80068007]
+  #_ REGISTER_OUT v4 [00018001, 10000000, 42568124, 00000000]

src/xenia/cpu/frontend/testing/instr_vcfsx.s

@@ -0,0 +1,20 @@
+test_vcfsx_1:
+  #_ REGISTER_IN v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 1.0, 1.5, 1.1, 1.9
+  vcfsx v3, v3, 0
+  blr
+  #_ REGISTER_OUT v3 [4e7e0000, 4e7f0000, 4e7e3333, 4e7fcccd]
+
+test_vcfsx_2:
+  #_ REGISTER_IN v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 1.0, 1.5, 1.1, 1.9
+  vcfsx v3, v3, 1
+  blr
+  #_ REGISTER_OUT v3 [4dfe0000, 4dff0000, 4dfe3333, 4dffcccd]
+
+test_vcfsx_3:
+  #_ REGISTER_IN v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 1.0, 1.5, 1.1, 1.9
+  vcfsx v3, v3, 10
+  blr
+  #_ REGISTER_OUT v3 [497e0000, 497f0000, 497e3333, 497fcccd]

src/xenia/cpu/frontend/testing/instr_vcmpxxfp.s

@@ -0,0 +1,32 @@
+test_vcmpxxfp_1:
+  #_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_IN v5 [3f800000, 3f800000, 3f800000, 3f800000]
+  vcmpeqfp. v3, v4, v5
+  mfocrf  r3, 2  # cr6
+  blr
+  #_ REGISTER_OUT v3 [ffffffff, ffffffff, ffffffff, ffffffff]
+  #_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_OUT v5 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_OUT r3 0x00000080
+
+test_vcmpxxfp_2:
+  #_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_IN v5 [3f800001, 3f800000, 3f800000, 3f800000]
+  vcmpeqfp. v3, v4, v5
+  mfocrf  r3, 2  # cr6
+  blr
+  #_ REGISTER_OUT v3 [00000000, ffffffff, ffffffff, ffffffff]
+  #_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_OUT v5 [3f800001, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_OUT r3 0x00000000
+
+test_vcmpxxfp_3:
+  #_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_IN v5 [3f800001, 3f800001, 3f800001, 3f800001]
+  vcmpeqfp. v3, v4, v5
+  mfocrf  r3, 2  # cr6
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_OUT v5 [3f800001, 3f800001, 3f800001, 3f800001]
+  #_ REGISTER_OUT r3 0x00000020

src/xenia/cpu/frontend/testing/instr_vctsxs.s

@@ -0,0 +1,32 @@
+test_vctsxs_1:
+  #_ REGISTER_IN v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 1.0, 1.5, 1.1, 1.9
+  vctsxs v3, v3, 0
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+
+test_vctsxs_2:
+  #_ REGISTER_IN v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 1.0, 1.5, 1.1, 1.9
+  vctsxs v3, v3, 1
+  blr
+  #_ REGISTER_OUT v3 [00000002, 00000003, 00000002, 00000003]
+
+test_vctsxs_3:
+  #_ REGISTER_IN v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 1.0, 1.5, 1.1, 1.9
+  vctsxs v3, v3, 2
+  blr
+  #_ REGISTER_OUT v3 [00000004, 00000006, 00000004, 00000007]
+
+test_vctsxs_4:
+  #_ REGISTER_IN v3 [42c83333, 43480000, 449a4000, c49a4000]
+  vctsxs v3, v3, 0
+  blr
+  #_ REGISTER_OUT v3 [00000064, 000000c8, 000004d2, fffffb2e]
+
+test_vctsxs_5:
+  #_ REGISTER_IN v3 [42c83333, 43480000, 449a4000, c49a4000]
+  vctsxs v3, v3, 1
+  blr
+  #_ REGISTER_OUT v3 [000000c8, 00000190, 000009a4, fffff65c]

src/xenia/cpu/frontend/testing/instr_vmaddfp.s

@@ -0,0 +1,39 @@
+test_vmaddfp_1:
+  #_ REGISTER_IN v4 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 1.0, 1.5, 1.1, 1.9
+  vmaddfp v3, v4, v4, v4
+  blr
+  #_ REGISTER_OUT v3 [40000000, 40700000, 4013d70a, 40b051eb]
+  #_ REGISTER_OUT v4 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 2.0, 3.75, 2.31, 5.51
+  # 40b051eb is actually 5.50999975, not 5.51?
+  # 40b051ec is 5.51
+
+test_vmaddfp_2:
+  #_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_IN v5 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_IN v6 [3f800000, 3f800000, 3f800000, 3f800000]
+  # 1.0, 1.5, 1.1, 1.9
+  vmaddfp v3, v4, v5, v6
+  blr
+  #_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_OUT v5 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_OUT v6 [3f800000, 3f800000, 3f800000, 3f800000]
+  
+test_vmaddfp_3:
+  # v4 = 5, 5, 1, 1
+  # v5 = 5, 5, 1, 1
+  # v6 = 1, 1, 1, 1
+  #_ REGISTER_IN v4 [40a00000, 40a00000, 3f800000, 3f800000]
+  #_ REGISTER_IN v5 [40a00000, 40a00000, 3f800000, 3f800000]
+  #_ REGISTER_IN v6 [3f800000, 3f800000, 3f800000, 3f800000]
+  # 1.0, 1.5, 1.1, 1.9
+  vmaddfp v3, v4, v5, v6
+  blr
+  # v3 = 26.0, 26.0, 2.0, 2.0
+  #_ REGISTER_OUT v3 [41d00000, 41d00000, 40000000, 40000000]
+  #_ REGISTER_OUT v4 [40a00000, 40a00000, 3f800000, 3f800000]
+  #_ REGISTER_OUT v5 [40a00000, 40a00000, 3f800000, 3f800000]
+  #_ REGISTER_OUT v6 [3f800000, 3f800000, 3f800000, 3f800000]
+  

src/xenia/cpu/frontend/testing/instr_vmrghb.s

@@ -0,0 +1,8 @@
+test_vmrghb_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  vmrghb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [00100111, 02120313, 04140515, 06160717]

src/xenia/cpu/frontend/testing/instr_vmrghh.s

@@ -0,0 +1,8 @@
+test_vmrghh_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  vmrghh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [00011011, 02031213, 04051415, 06071617]

src/xenia/cpu/frontend/testing/instr_vmrghw.s

@@ -0,0 +1,8 @@
+test_vmrghw_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  vmrghw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [00010203, 10111213, 04050607, 14151617]

src/xenia/cpu/frontend/testing/instr_vmrglb.s

@@ -0,0 +1,8 @@
+test_vmrglb_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  vmrglb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [08180919, 0a1a0b1b, 0c1c0d1d, 0e1e0f1f]

src/xenia/cpu/frontend/testing/instr_vmrglh.s

@@ -0,0 +1,8 @@
+test_vmrglh_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  vmrglh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [08091819, 0a0b1a1b, 0c0d1c1d, 0e0f1e1f]

src/xenia/cpu/frontend/testing/instr_vmrglw.s

@@ -0,0 +1,8 @@
+test_vmrglw_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  vmrglw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [08090a0b, 18191a1b, 0c0d0e0f, 1c1d1e1f]

src/xenia/cpu/frontend/testing/instr_vmsum4fp128.s

@@ -0,0 +1,8 @@
+test_vmsum4fp128_1:
+  #_ REGISTER_IN v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  #_ REGISTER_IN v4 [40000000, 40700000, 4013d70a, 40b051eb]
+  vmsum4fp128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  #_ REGISTER_OUT v4 [40000000, 40700000, 4013d70a, 40b051eb]
+  #_ REGISTER_OUT v5 [41A5147B, 41A5147B, 41A5147B, 41A5147B]

src/xenia/cpu/frontend/testing/instr_vperm.s

@@ -0,0 +1,44 @@
+test_vperm_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
+  vperm v6, v3, v4, v5
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v6 [00000000, 00000000, 00000000, 00000000]
+
+test_vperm_2:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [01010101, 01010101, 01010101, 01010101]
+  vperm v6, v3, v4, v5
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v6 [01010101, 01010101, 01010101, 01010101]
+
+test_vperm_3:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [11111111, 11111111, 11111111, 11111111]
+  vperm v6, v3, v4, v5
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [11111111, 11111111, 11111111, 11111111]
+  #_ REGISTER_OUT v6 [11111111, 11111111, 11111111, 11111111]
+
+test_vperm_4:
+  # try with > 32b values (should mod)
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [21212121, 21212121, 21212121, 21212121]
+  vperm v6, v3, v4, v5
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [21212121, 21212121, 21212121, 21212121]
+  #_ REGISTER_OUT v6 [01010101, 01010101, 01010101, 01010101]

src/xenia/cpu/frontend/testing/instr_vpermwi128.s

@@ -0,0 +1,35 @@
+test_vpermwi128_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  # to 0,1,2,3
+  # vpermwi128 v4, v3, 0x1B
+  .long 0x189B1A10
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vpermwi128_2:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  # to 3,2,1,0
+  # vpermwi128 v4, v3, 0xE4
+  .long 0x18841BD0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [0C0D0E0F, 08090A0B, 04050607, 00010203]
+
+test_vpermwi128_3:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  # to 0,0,0,0
+  # vpermwi128 v4, v3, 0
+  .long 0x18801A10
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [00010203, 00010203, 00010203, 00010203]
+
+test_vpermwi128_4:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  # to 3,3,3,3
+  # vpermwi128 v4, v3, 0xFF
+  .long 0x189F1BD0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [0C0D0E0F, 0C0D0E0F, 0C0D0E0F, 0C0D0E0F]

src/xenia/cpu/frontend/testing/instr_vpkd3d128.s

@@ -0,0 +1,240 @@
+# vpkd3d128 dest, src, type, mask, shift
+# type:
+#   0 = PACK_TYPE_D3DCOLOR
+#   1 = PACK_TYPE_SHORT_2
+#   3 = PACK_TYPE_FLOAT16_2
+#   5 = PACK_TYPE_FLOAT16_4
+# mask:
+#   must not be zero
+#   1 = 00000000 00000000 00000000 FFFFFFFF
+#   2 = 00000000 00000000 FFFFFFFF FFFFFFFF
+#   3 = same as 2? except mask3/shift3
+# shift:
+#   0 = no shift
+#   1 = shift left by one word
+#   2 ...
+#   3 ...
+# special case: mask3/shift3 = 00000000 00000000 00000000 FFFFFFFF
+
+# vpkd3d128 is broken in binutils, so these are hand coded
+
+test_vpkd3d128_d3dcolor_invalid_0:
+  #_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 1, 0
+  .long 0x18811E10
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]
+test_vpkd3d128_d3dcolor_invalid_1:
+  #_ REGISTER_IN v3 [40800000, 40000000, C2F60000, 4B3BDF83]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 1, 0
+  .long 0x18811E10
+  blr
+  #_ REGISTER_OUT v3 [40800000, 40000000, C2F60000, 4B3BDF83]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFF0000]
+
+test_vpkd3d128_d3dcolor_1_0:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 1, 0
+  .long 0x18811E10
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+test_vpkd3d128_d3dcolor_1_1:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 1, 1
+  .long 0x18811E50
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 04010203, CDCDCDCD]
+test_vpkd3d128_d3dcolor_1_2:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 1, 2
+  .long 0x18811E90
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, 04010203, CDCDCDCD, CDCDCDCD]
+test_vpkd3d128_d3dcolor_1_3:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 1, 3
+  .long 0x18811ED0
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+
+test_vpkd3d128_d3dcolor_2_0:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 2, 0
+  .long 0x18821E10
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203]
+test_vpkd3d128_d3dcolor_2_1:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 2, 1
+  .long 0x18821E50
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD]
+test_vpkd3d128_d3dcolor_2_2:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 2, 2
+  .long 0x18821E90
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD]
+test_vpkd3d128_d3dcolor_2_3:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 2, 3
+  .long 0x18821ED0
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+
+test_vpkd3d128_d3dcolor_3_0:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 3, 0
+  .long 0x18831E10
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203]
+test_vpkd3d128_d3dcolor_3_1:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 3, 1
+  .long 0x18831E50
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD]
+test_vpkd3d128_d3dcolor_3_2:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 3, 2
+  .long 0x18831E90
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD]
+test_vpkd3d128_d3dcolor_3_3:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 3, 3
+  .long 0x18831ED0
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]
+
+
+test_vpkd3d128_short2_invalid_0:
+  #_ REGISTER_IN v3 [43817E00, C37CFC00, 42A23EC8, 403DB757]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 1, 1, 0
+  .long 0x18851E10
+  blr
+  #_ REGISTER_OUT v3 [43817E00, C37CFC00, 42A23EC8, 403DB757]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
+test_vpkd3d128_short2_invalid_1:
+  #_ REGISTER_IN v3 [412FDF00, C09FBE00, 42A23EC8, 403DB757]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 1, 1, 0
+  .long 0x18851E10
+  blr
+  #_ REGISTER_OUT v3 [412FDF00, C09FBE00, 42A23EC8, 403DB757]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
+
+test_vpkd3d128_short2_0:
+  #_ REGISTER_IN v3 [40407FFF, 403F8001, 00000000, 00000000]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 1, 1, 0
+  .long 0x18851E10
+  blr
+  #_ REGISTER_OUT v3 [40407FFF, 403F8001, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
+test_vpkd3d128_short2_1:
+  #_ REGISTER_IN v3 [40404000, 403FC000, 40400003, 403F8001]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 1, 1, 0
+  .long 0x18851E10
+  blr
+  #_ REGISTER_OUT v3 [40404000, 403FC000, 40400003, 403F8001]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 4000C000]
+test_vpkd3d128_short2_2:
+  #_ REGISTER_IN v3 [4040FFFE, 403FF333, 42A23EC8, 403DB757]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 1, 1, 0
+  .long 0x18851E10
+  blr
+  #_ REGISTER_OUT v3 [4040FFFE, 403FF333, 42A23EC8, 403DB757]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFFF333]
+
+
+test_vpkd3d128_uint_2101010_0:
+  #_ REGISTER_IN v3 [B8FF8000, B8FF8000, C04001FF, 4E9A5A5A]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 2, 1, 0
+  .long 0x18891E10
+  blr
+  #_ REGISTER_OUT v3 [B8FF8000, B8FF8000, C04001FF, 4E9A5A5A]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, E0180601]
+test_vpkd3d128_uint_2101010_1:
+  #_ REGISTER_IN v3 [42C80000, C2C80000, 40400000, 3F800000]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 2, 1, 0
+  .long 0x18891E10
+  blr
+  #_ REGISTER_OUT v3 [42C80000, C2C80000, 40400000, 3F800000]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 000805FF]
+test_vpkd3d128_uint_2101010_2:
+  #_ REGISTER_IN v3 [3F000000, BF000000, 3F800000, 00000000]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 2, 1, 0
+  .long 0x18891E10
+  blr
+  #_ REGISTER_OUT v3 [3F000000, BF000000, 3F800000, 00000000]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 20180601]
+
+
+test_vpkd3d128_float16_2_invalid_0:
+  #_ REGISTER_IN v3 [3FC00000, BFC00000, 42A23EC8, 403DB757]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 3, 1, 0
+  .long 0x188D1E10
+  blr
+  #_ REGISTER_OUT v3 [3FC00000, BFC00000, 42A23EC8, 403DB757]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3E00BE00]
+test_vpkd3d128_float16_2_0:
+  #_ REGISTER_IN v3 [3F000000, BF000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 3, 1, 0
+  .long 0x188D1E10
+  blr
+  #_ REGISTER_OUT v3 [3F000000, BF000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3800B800]
+
+
+test_vpkd3d128_float16_4_invalid_0:
+  #_ REGISTER_IN v3 [3FC00000, BFC00000, 3FC00000, BFC00000]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 5, 2, 0
+  .long 0x18961E10
+  blr
+  #_ REGISTER_OUT v3 [3FC00000, BFC00000, 3FC00000, BFC00000]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 3E00BE00, 3E00BE00]
+test_vpkd3d128_float16_4_0:
+  #_ REGISTER_IN v3 [3F000000, BF000000, 3F000000, BF000000]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 5, 2, 0
+  .long 0x18961E10
+  blr
+  #_ REGISTER_OUT v3 [3F000000, BF000000, 3F000000, BF000000]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 3800B800, 3800B800]

src/xenia/cpu/frontend/testing/instr_vpkshss.s

@@ -0,0 +1,17 @@
+test_vpkshss_0:
+  #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
+  vpkshss v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
+  #_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vpkshss_1:
+  #_ REGISTER_IN v3 [7FFF8000, 00020003, 00040005, 00060007]
+  #_ REGISTER_IN v4 [7FFF8000, 000A000B, 000C000D, 000E000F]
+  vpkshss v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFF8000, 00020003, 00040005, 00060007]
+  #_ REGISTER_OUT v4 [7FFF8000, 000A000B, 000C000D, 000E000F]
+  #_ REGISTER_OUT v5 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]

src/xenia/cpu/frontend/testing/instr_vpkswss.s

@@ -0,0 +1,17 @@
+test_vpkswss_0:
+  #_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_IN v4 [00000005, 00000006, 00000007, 00000008]
+  vpkswss v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_OUT v4 [00000005, 00000006, 00000007, 00000008]
+  #_ REGISTER_OUT v5 [00010002, 00030004, 00050006, 00070008]
+
+test_vpkswss_1:
+  #_ REGISTER_IN v3 [7FFFFFFF, 80000000, 00000000, 00000004]
+  #_ REGISTER_IN v4 [7FFFFFFF, 80000000, 00000000, 00000008]
+  vpkswss v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFFFFFF, 80000000, 00000000, 00000004]
+  #_ REGISTER_OUT v4 [7FFFFFFF, 80000000, 00000000, 00000008]
+  #_ REGISTER_OUT v5 [7FFF8000, 00000004, 7FFF8000, 00000008]

src/xenia/cpu/frontend/testing/instr_vrfin.s

@@ -0,0 +1,13 @@
+test_vrfin_1:
+  #_ REGISTER_IN v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 1.0, 1.5, 1.1, 1.9 -> 1.0, 2.0, 1.0, 2.0
+  vrfin v3, v3
+  blr
+  #_ REGISTER_OUT v3 [3f800000, 40000000, 3f800000, 40000000]
+
+test_vrfin_2:
+  #_ REGISTER_IN v3 [bf800000, bfc00000, bf8ccccd, bff33333]
+  # -1.0, -1.5, -1.1, -1.9 -> -1.0, -2.0, -1.0, -2.0
+  vrfin v3, v3
+  blr
+  #_ REGISTER_OUT v3 [bf800000, c0000000, bf800000, c0000000]

src/xenia/cpu/frontend/testing/instr_vrlimi128.s

@@ -0,0 +1,75 @@
+test_vrlimi128_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+
+test_vrlimi128_2:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0xF, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vrlimi128_3:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  # assember is busted here:
+  # vrlimi128 v4, v3, 0xF, 1
+  .long 0x188f1f50
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [04050607, 08090A0B, 0C0D0E0F, 00010203]
+
+test_vrlimi128_4:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0xF, 2
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [08090A0B, 0C0D0E0F, 00010203, 04050607]
+
+test_vrlimi128_5:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  # assember is busted here:
+  # vrlimi128 v4, v3, 0xF, 3
+  .long 0x188f1fd0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [0C0D0E0F, 00010203, 04050607, 08090A0B]
+
+test_vrlimi128_6:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0x8, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [00010203, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+
+test_vrlimi128_7:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0x4, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [CCCCCCCC, 04050607, CCCCCCCC, CCCCCCCC]
+
+test_vrlimi128_8:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0x2, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [CCCCCCCC, CCCCCCCC, 08090A0B, CCCCCCCC]
+
+test_vrlimi128_9:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0x1, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, 0C0D0E0F]

src/xenia/cpu/frontend/testing/instr_vsel.s

@@ -0,0 +1,29 @@
+test_vsel_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
+  vsel v5, v3, v4, v5
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vsel_2:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vsel v5, v3, v4, v5
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+
+test_vsel_3:
+  #_ REGISTER_IN v3 [0C010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [1D111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [10101010, 10101010, 10101010, 10101010]
+  vsel v5, v3, v4, v5
+  blr
+  #_ REGISTER_OUT v3 [0C010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [1D111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [1C111213, 14151617, 18191A1B, 1C1D1E1F]

src/xenia/cpu/frontend/testing/instr_vsl.s

@@ -0,0 +1,23 @@
+test_vsl_1:
+  #_ REGISTER_IN v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
+  vsl v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [EFEFEFEF, EFEFEFEF, EFEFEFEF, EFEFEFE0]
+  #_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
+
+test_vsl_2:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
+  vsl v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [01122334, 45566778, 899AABBC, CDDEEFF0]
+  #_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
+
+test_vsl_3:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707]
+  vsl v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [089119A2, 2AB33BC4, 4CD55DE6, 6EF77F80]
+  #_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]

src/xenia/cpu/frontend/testing/instr_vslb.s

@@ -0,0 +1,39 @@
+test_vslb_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vslb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vslb_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vslb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+
+test_vslb_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707]
+  vslb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]
+
+test_vslb_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808]
+  vslb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808]
+
+test_vslb_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [09090909, 09090909, 09090909, 09090909]
+  vslb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v4 [09090909, 09090909, 09090909, 09090909]

src/xenia/cpu/frontend/testing/instr_vsldoi.s

@@ -0,0 +1,29 @@
+test_vsldoi_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
+  vsldoi v5, v3, v4, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vsldoi_2:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
+  vsldoi v5, v3, v4, 1
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [01020304, 05060708, 090A0B0C, 0D0E0F10]
+
+test_vsldoi_3:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
+  vsldoi v5, v3, v4, 0xF
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [0F101112, 13141516, 1718191A, 1B1C1D1E]