Commit Graph

622 Commits

Author SHA1 Message Date
Herman S.
3e3aee1ef2 [App] Update title to show apu and remove vulkan incomplete warning 2026-02-17 23:50:40 +09:00
Herman S.
5897de3eaf [Vulkan] Implement tiled_shared_memory for resolution scaling
Adds support for >3x resolution scaling to vulkan by implementing
sparse scaled resolve similar to the d3d12 implementation.
2026-02-17 21:31:25 +09:00
Herman S.
a092551735 [Vulkan/D3D12] Validate upload range bounds before vastcpy
The D3D12 backend's existing check only validated the last page of the
range. The Vulkan backend had no check at all and did not respect the
gpu_allow_invalid_upload_range cvar. Both now verify start and
end pages are mapped before copying, preventing access violations when
games reference unmapped guest physical memory during transitions.
2026-02-17 21:22:48 +09:00
Herman S.
ef505fbe3d [Vulkan] add no_discard_stencil_in_transfer_pipelines support 2026-02-17 17:54:01 +09:00
Herman S.
434644c301 Merge commit 'f2fabfdf0' into canary_experimental
Sync changes from master up to before the recent GPU changes, those will be
merged later
2026-02-17 16:59:38 +09:00
goldislead
1a9613705d Rework max anisotropy override to sampler creation (D3D12/Vulkan)
Revert ac6fd65 fetch additions and implement context-sensitive AF override.
2026-02-07 17:47:12 +01:00
Triang3l
0f23f05683 [GPU] Simplify local X offsetting with resolution scaling
Switch between even and odd 16-byte element sequences along X by simply
flipping a bit rather than going to a different resolution-scaled group of
pixels, by increasing the size of the group within the constraints imposed
by tiling.
2026-01-13 23:14:15 +03:00
Triang3l
fe1fd36137 [D3D12/Vulkan] Simplify host GPU fence management
Replace the `SubmissionTracker`s with new `GPUCompletionTimeline`s with a
more unified interface (using a base class), and without the internal logic
for queue ownership transfers since that idea was scrapped during the
development of the `Presenter`.

Also use this fence management logic for GPU emulation, though without
architectural reworks for now, just on the bottom level.

Still very messy, but can be cleaned up in further GPU command processor
and presenter reworks.
2025-12-14 21:24:38 +03:00
yippeeeyay
2b77c4c08a [D3D12] Simplify Intel Arc GPU checking 2025-12-07 19:09:36 +01:00
Gliniak
038b11a537 [GPU] Removed nvapi
- According to reports d3d12_nvapi_use_driver_heap_priorities give no benefit
2025-12-05 21:54:06 +01:00
Gliniak
78e753ef52 [GPU] Added config option to enable/disable invalid memory uploads 2025-12-02 22:34:39 +01:00
Herman S.
e2c33686cc [GPU] Double-buffer readback_resolve.
Introduce "fast" readback resolve that reads from previous frame's
resolve buffers, quick swap between buffers each frame to avoid
copies so minimal performance impact and mostly correct bahavior.
Checks if previous frame had a buffer for the current resolve and
falls through to the slow path, which also allows to support
"screenshot" features in the games that do that without stalling
on normal resolve operations.

Re-enabled readback_memexport as separate feature, was previously
bundled with readback_resolve (probably not intentionally) and
ensures destination address is writeable to avoid memory access
related crashes and unnecessary work.

readback_resolve cvar changes from bool to string ternary with
"none", "fast" and "full" options, defaulting to the new "fast"
mode.
2025-12-01 17:38:34 +01:00
Gliniak
1bf98e9354 [D3D12] Restored memory access safeguard 2025-11-18 23:01:28 +01:00
Herman S.
4644657e83 [Vulkan] Implement readback_resolve for vulkan 2025-10-23 07:54:38 +02:00
Triang3l
0b2ffa3148 [GPU] Change texture load cbuffer to push constants
Simplify the code, eliminating the need for supporting requesting cbuffers
for anything other than guest draw command execution.
2025-08-20 12:46:26 +03:00
Gliniak
419c0149c9 [Base] Post merge fixes 2025-08-15 18:06:57 +02:00
Gliniak
c4bd676c5e Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2025-08-15 15:37:50 +02:00
Triang3l
b5432ab83f [Vulkan] Refactoring and fixes for VulkanProvider and related areas
Enable portability subset physical device enumeration.

Don't use Vulkan 1.1+ logical devices on Vulkan 1.0 instances due to the
VkApplicationInfo::apiVersion specification.

Make sure all extension dependencies are enabled when creating a device.

Prefer exposing feature support over extension support via the device
interface to avoid causing confusion with regard to promoted extensions
(especially those that required some features as extensions, but had those
features made optional when they were promoted).

Allow creating presentation-only devices, not demanding any optional
features beyond the basic Vulkan 1.0, for use cases such as internal tools
or CPU rendering.

Require the independentBlend feature for GPU emulation as working around is
complicated, while support is almost ubiquitous.

Move the graphics system initialization fatal error message to xenia_main
after attempting to initialize all implementations, for automatic fallback
to other implementations in the future.

Log Vulkan driver info.

Improve Vulkan debug message logging, enabled by default.

Refactor code, with simplified logic for enabling extensions and layers.
2025-08-14 23:44:21 +03:00
Triang3l
a06be03f1b [GPU] Cleanup definitions of some registers
VS/PS_NUM_REG is 6-bit on Adreno 200, and games aren't seen using the
bit 7 to indicate that no GPRs are used. It's not clear why Freedreno
configures it this way.

Some texture fetch fields were deprecated or moved during the development
of the Xenos, reflect that in the comments.

Add definitions of the registers configuring the conversion of vertex
positions to fixed-point. Although there isn't much that can be done with
it when emulating using PC GPU APIs, there are some places in Xenia that
wrongly (though sometimes deliberately, for results closer to the behavior
of the host GPU) assume that the conversion works like in Direct3D 10+,
however the Xenos supports only up to 4 subpixel bits rather than 8. The
effects of this difference are largely negligible, though.

Also add more detailed info about register references and differences from
other ATI/AMD GPUs for potential future contributors.
2025-08-06 13:21:19 +03:00
Gliniak
37e3fe9eb6 [D3D12] Default to RTV on Intel ARC GPUs 2025-08-03 22:26:39 +02:00
Margen67
4cb783bf22 Header cleanup 2025-07-19 14:42:21 -07:00
Gliniak
3ba31d9f9a Revert "[D3D12] Changed default resource state based on GPU Validation"
This causes unexpected artifacts on 10 series Nvidia GPUs

This reverts commit 7566871220.
2025-05-04 08:57:42 +02:00
Gliniak
7797adf5f2 [UI] Fixed issue with freezing/crashing (BSOD) UI caused by incorrect fence 2025-04-26 11:17:27 +02:00
Gliniak
8f647c548d [D3D12] Removed GBV warning related to incorrect blend setup in specific conditions 2025-04-24 19:30:57 +02:00
Gliniak
7566871220 [D3D12] Changed default resource state based on GPU Validation
- This prevents GBV from spamming warnings
2025-04-22 19:31:31 +02:00
Gliniak
31d715d100 [Premake] Removed unused/unnecessary subprojects.
- Testing currently doesn't work
- VFS Dump is unused. You can use internal function for it
- Demos are only for fun
- Trace Dump & Trace Viewer (unsure, but ok)

You can re-enable them by changing values: enableTests and enableMiscSubprojects in main premake file.

In the future there should be xb command support to overwrite them
2025-04-15 09:04:16 +02:00
Gliniak
7298536d46 [HID] Added support for Xbox 360 Skylanders Portal
- This requires Zadig for installation of WinUSB driver for portal
2025-04-14 21:44:49 +02:00
Xphalnos
47f327e848 [Misc] Replaced const with constexpr where possible 2025-04-08 19:32:17 +02:00
Xphalnos
7479ccc292 [Misc] Fix Some Warnings on Clang Build with Windows + Adding constexpr 2025-03-27 17:52:18 +01:00
Xphalnos
5f918ef28d [Misc] Replaced const with constexpr where possible 2025-03-25 19:50:37 +01:00
Gliniak
0474053931 [GPU] Improvements to GPU settings modification
- Renamed CommonGPUSetting to GPUSetting
- Removed readback_resolve and memexport from d3d12 exclusive option. In the future it will be available for Vulkan too.
- Removed unused enum class: gpu_cvar
- Removed OS specific code from emulator_window
2025-01-17 20:40:53 +01:00
Gliniak
a295ec1bbd [Base] Removed useless path_to_utf8 conversion while using fmt
Default filesystem::path formatter was added to fmt around 2022
2024-12-13 19:04:31 +01:00
Gliniak
3318ab5d4c [3PP] Uplifted FMT version and adjusted messages 2024-12-12 20:28:11 +01:00
Gliniak
3ac98ebfba [Static Analysis] Resolved some issues mentioned in Alexandr-u report 2024-11-02 19:08:34 +01:00
Gliniak
5f5be06680 [Memory] Preallocate whole physical range for GPU.
Seems like GPU has direct access to whole RAM and can request anything.

Removed check for page access as all pages are now available for gpu
2024-09-01 22:21:28 +02:00
Gliniak
feb88ee6b1 [GPU] Check page access only once for specific range 2024-08-10 21:33:56 +02:00
Gliniak
1864f3d9f2 [D3D12] Redesigned page access for gpu buffer allocation 2024-08-10 20:58:53 +02:00
NicknineTheEagle
c4e930ed4c Proper 4:3 support 2024-07-01 08:55:15 +02:00
Gliniak
b3f2ab0e96 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2024-05-31 22:43:59 +02:00
Triang3l
376bad5056 [GPU] Remove register reinterpret_casts + WAIT_REG_MEM volatility
Hopefully prevents some potential #1971-like situations.

WAIT_REG_MEM's implementation also allowed the compiler to load the value
only once, which caused an infinite loop with the other changes in the
commit (even in debug builds), so it's now accessed as volatile. Possibly
it would be even better to replace it with some (acquire/release?) atomic
load/store some day at least for the registers actually seen as
participating in those waits.

Also fixes the endianness being handled only on the first wait iteration in
WAIT_REG_MEM.
2024-05-12 17:28:17 +03:00
Gliniak
3d4bdc9023 Revert "[GPU] Resolved memory leak in RTV in pipeline creation"
This reverts commit e8dbb65fc1.
2024-03-16 11:07:45 +01:00
Gliniak
e8dbb65fc1 [GPU] Resolved memory leak in RTV in pipeline creation 2024-03-15 17:38:30 +01:00
Gliniak
b9061e6292 [LINT] Linted files + Added lint job to CI 2024-03-12 19:19:30 +01:00
Gliniak
ce9a82ccf8 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2023-09-01 18:20:29 +02:00
Gliniak
2a4d7feaae [GPU] Unified clear_memory_page_state to be used in D3D12 & Vulkan 2023-08-06 21:56:35 +02:00
Triang3l
ed64e3072b [GPU] Remove implicit bool cast in memexport checks 2023-05-05 21:38:45 +03:00
Triang3l
53f98d1fe6 [GPU/D3D12] Memexport from anywhere in control flow + 8/16bpp memexport
There's no limit on the number of memory exports in a shader on the real
Xenos, and exports can be done anywhere, including in loops. Now, instead
of deferring the exports to the end of the shader, and assuming that export
allocs are executed only once, Xenia flushes exports when it reaches an
alloc (allocs terminate memory exports on Xenos, as well as individual ALU
instructions with `serialize`, but not handling this case for simplicity,
it's only truly mandatory to flush memory exports before starting a new
one), the end of the shader, or a pixel with outstanding exports is killed.

To know which eM# registers need to be flushed to the memory, traversing
the successors of each exec potentially writing any eM#, and specifying
that certain eM# registers might have potentially been written before each
reached control flow instruction, until a flush point or the end of the
shader is reached.

Also, some games export to sub-32bpp formats. These are now supported via
atomic AND clearing the bits of the dword to replace followed by an atomic
OR inserting the new byte/short.
2023-05-05 21:32:02 +03:00
chss95cs@gmail.com
27c4cef1b5 Added logger flags, for selectively disabling categories of logging (cpu, apu, kernel). Need to make more log messages make use of these flags.
The "close window" keyboard hotkey (Guide-B) now toggles between loglevel -1 and the loglevel set in your config.
Added LoggerBatch class, which accumulates strings into the threads scratch buffer. This is only intended to be used for very high frequency debug logging. if it exhausts the thread buffer, it just silently stops.
Cleaned nearly 8 years of dust off of the pm4 packet disassembler code, now supports all packets that the command processor supports.
Added extremely verbose logging for gpu register writes. This is not compiled in outside of debug builds, requires LogLevel::Debug and log_guest_driven_gpu_register_written_values = true.
Added full logging of all PM4 packets in the cp. This is not compiled in outside of debug builds, requires LogLevel::Debug and disassemble_pm4.
Piggybacked an implementation of guest callstack backtraces using the stackpoints from enable_host_guest_stack_synchronization. If enable_host_guest_stack_synchronization = false, no backtraces can be obtained.
Added log_ringbuffer_kickoff_initiator_bts. when a thread updates the cp's read pointer, it dumps the backtrace of that thread
Changed the names of the gpu registers CALLBACK_ADDRESS and CALLBACK_CONTEXT to the correct names.
Added a note about CP_PROG_COUNTER
Added CP_RB_WPTR to the gpu register table
Added notes about CP_RB_CNTL and CP_RB_RPTR_ADDR. Both aren't necessary for HLE
Changed name of UNKNOWN_0E00 gpu register to TC_CNTL_STATUS. Games only seem to write 1 to it (L2 invalidate)
2023-04-16 12:42:42 -04:00
Gliniak
5e0c67438c Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2023-04-09 17:28:04 +02:00
Gliniak
7fce8fce9d Revert "[D3D12] Added workaround for broken Geometry Shader in AMD 7900 Series GPU"
This reverts commit 2afd2cc4d6.
2023-04-09 17:27:55 +02:00