- add SIGTRAP handling
- remove per-test dots and print per suite instead
- refactor test loop from collecting all tests to iterating suites
- fix logging up output
d37c22aa replaced skylander with the new portal HID library but
missed updating three CMakeLists.txt files. No replacement needed
since xenia-hid already links xenia-hid-portal transitively.
Generate per-function CIE+FDE records and register them via
__register_frame so the C++ exception unwinder can propagate through
JIT frames. Replace setjmp/longjmp fiber reentry with throw/catch
on Linux to ensure destructors and RAII guards run during fiber
stack switches.
std::ifstream read of /proc/self/maps is not async-signal-safe and runs
on every access violation fault. Skip the race-condition check and go
straight to the callback, which handles cleared watches correctly.
Fixes severe performance issues seen in MFSMW, MCLA, etc.
BaseHeap::Dispose() walks the page table and calls
DeallocFixed(addr, 0, kRelease) for every allocated page region.
These addresses are within file-backed view mappings (i.e. guest memory).
On Windows, VirtualFree on file-mapped pages silently returns FALSE.
On POSIX, the code hit assert_always() and crashed. Changed to return false
to match Windows behavior.
Memory leaks from munmap(addr, 0):
Callers passed length=0 to DeallocFixed(kRelease). On Windows this works because
VirtualFree(addr, 0, MEM_RELEASE) means "release the entire region" — Windows
ignores the length parameter for MEM_RELEASE and always frees the whole
allocation. On POSIX, munmap(addr, 0) fails with EINVAL, so the memory was
silently leaked every time.
On Linux, these instructions appear to use A format (FRA, FRB, FRT)
instead of the standard X format (RA, RB, RT). Need to verify if this
is needed on Windows or is Linux specific.
Implement SNaN detection and FPSCR exception tracking so that Rc=1 FPU
instructions (fadds., fmadds., etc.) correctly update CR1 with FPSCR
exception summary bits (FX, FEX, VX, OX). Previously these were
hardcoded to zero. Enable ~2k tests that were previously disabled.
Add 3-bit VC field to VX128_2 format structure to support
instructions like vperm128 that use 4 distinct vector operands.
The VC field occupies bits 6-8 of the instruction encoding.
mcrfs: Implement Move CR from FPSCR instruction
Copies a 4-bit FPSCR field to CR and clears the FPSCR exception bits.
mffsx: Fix Rc bit handling
Properly update CR1 from FPSCR when Rc=1 instead of returning error.
Previously treated Rc=1 as unimplemented.
fcfidx: Fix Rc field access
Use i.X.Rc instead of i.A.Rc for correct instruction format.
fcfid uses X format, not A format.
Implement mcrxr (Move to Condition Register from XER).
Copies XER condition bits (SO, OV, CA) to a CR field and
clears those bits in XER. This was previously unimplemented.
Correct mfvscr and mtvscr to use VX format instead of VX128_1.
These instructions operate on the standard Altivec VSCR register,
not VMX128 extended registers. The previous VX128_1 format was
incorrectly accessing the RB field instead of VD/VB.
Add round-to-nearest-even to the fast float16 pack path by folding a
0xFFF rounding bias into XMMF16PackLCPI0 and extracting bit 13 of the
source as the tie-breaker, matching the software fallback behavior.
Fix PACK_SHORT_2 test to use pre-biased float input (0x40400000 = 3.0)
as the hardware expects, rather than raw 0.0f which is out of range.
The loop conditions `n < 8 - n` and `n < 4 - n` terminated early,
only checking the first half of elements. This caused EmitInt16 and
EmitInt32 to incorrectly take the uniform shift path when trailing
elements had different shift amounts.
Resolves potential issues in SHL, SHR, and SHA.
When performing unsigned multiplication on Linux/GCC,
the code incorrectly cast constant.i64 (which is a signed int64_t)
to unsigned __int128. This caused sign extension when
the value should be treated as unsigned.
Current implementation has an off by 1 in rounding, should
round up to even but doesn't. Need to figure out how to implement
it properly so just leaving the software version here for later
verification.
