Triang3l
c794d0d538
[GPU] DC_LUT_RW_INDEX/WRITE_EN_MASK + gamma ramp and registers in traces
2022-05-05 13:10:29 +03:00
Triang3l
6fcf9d21fe
[D3D12] Point sprite size fixes, point/line bits in PsParamGen
2022-05-03 16:15:16 +03:00
Triang3l
0fd578cafd
[GPU] Get unclipped draw height by running VS on the CPU
2022-04-28 22:25:25 +03:00
Triang3l
b2b1d7b518
[GPU] More accurate vertex kill + PsParamGen/point documentation
2022-04-27 23:10:56 +03:00
Triang3l
fdec0ab332
[Code] Make union usage more consistent
2021-11-03 20:45:09 +03:00
Triang3l
28fec845d5
[GPU] Document memexport/resolve formats with more details
2021-10-22 20:00:41 +03:00
Triang3l
e720e0a540
[Code] Remove game names from code comments (most of at least)
2021-09-05 21:27:40 +03:00
Triang3l
458e4e1a31
[GPU] Official RB name from RDNA/GCN/TeraScale/Xenos docs/news
2021-07-01 23:43:01 +03:00
Triang3l
22ee200f3e
[GPU] Use polygon mode only for DualMode, not non-Disabled
2021-06-07 16:40:01 +03:00
Triang3l
538aa91015
[GPU] Primitive processor with Vulkan 1.0 base cases, 24-bit indices and clamping
2021-06-04 23:57:46 +03:00
Triang3l
f39020700a
[GPU] Cleanup: XEPACKED -> static_assert_size/alignas
2021-05-16 14:03:36 +03:00
Triang3l
330beaf552
[GPU] Screen scissor alongside window scissor
2021-05-04 22:54:05 +03:00
Triang3l
e6fa0ad139
[GPU] Dynamic r# count via shader modifications + refactoring
2020-12-19 16:14:54 +03:00
Triang3l
b106aa88e6
[GPU] Complete some register bitfield declarations
2020-12-12 20:01:41 +03:00
Joel Linn
f6dc9ad517
[GPU] Skip viz-query geometry (if marked).
...
Document research about viz queries.
v2: Remove viz status unions and move comments to register definitions.
Add contributors to TODOs.
v3: Comment out unused variables.
Add TODO for correctly dropping draw calls with memexport.
Register comment formatting.
2020-11-21 21:55:52 +03:00
Triang3l
bd5f77bc3b
[GPU] Common resolve code based on compute shaders, swap MSAA samples 1 and 2, change ROV write rounding, random refactoring
2020-08-09 21:33:10 +03:00
Triang3l
4bb0ca0e09
[GPU] Move all xenos.h to gpu::xenos, disambiguate Dimension/TextureDimension
2020-07-11 15:54:22 +03:00
Triang3l
1547b9df41
[D3D12] Interpolation at centroid
2020-07-08 23:20:36 +03:00
Triang3l
829c6ee2b0
[D3D12] Dithered alpha to coverage
2020-07-07 23:09:53 +03:00
Triang3l
64a83af137
[DXBC] Cleanup StartPixelShader, always_reads_mask, and ps_param_gen overall
2020-04-25 00:20:27 +03:00
Triang3l
90b772a330
[GPU] Set VGT_DRAW_INITIATOR and use major mode from it
2020-02-24 23:27:25 +03:00
Triang3l
a9ed73bdd1
[GPU] Remove most hardcoded register/instruction layouts from common and D3D12 code
2019-10-20 19:40:37 +03:00
Triang3l
f83269cf8c
[GPU] Refactor: Register structs in D3D12CommandProcessor and some other places
2019-10-19 23:32:38 +03:00
Triang3l
c4f80aac0d
[D3D12] EDRAM layout of a rectangle and other resolve stuff
2018-08-22 17:33:43 +03:00
DrChat
4cfe1e3203
[Vulkan] Support window scissor in IssueCopy
2017-12-21 22:38:35 -06:00
DrChat
cce5182725
Vulkan: Fix swap on resolve (off by one!)
...
Clean up part of IssueCopy
2017-08-07 23:34:50 -05:00
Dr. Chat
0c2e0e4119
RenderCache: Update to register bitfield structs
2017-03-13 17:54:41 -05:00
Dr. Chat
76f6aa7c90
Xenos: Add a few bitfield registers to registers.h
2017-02-22 16:17:03 -06:00
