72 lines
2.5 KiB
ArmAsm
72 lines
2.5 KiB
ArmAsm
test_vrlw_1:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vrlw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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test_vrlw_2:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
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vrlw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
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test_vrlw_3:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [0000001F, 0000001F, 0000001F, 0000001F]
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vrlw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [0000001F, 0000001F, 0000001F, 0000001F]
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test_vrlw_4:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00000020, 00000020, 00000020, 00000020]
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vrlw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [00000020, 00000020, 00000020, 00000020]
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test_vrlw_5:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00000021, 00000021, 00000021, 00000021]
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vrlw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [00000021, 00000021, 00000021, 00000021]
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test_vrlw_6:
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#_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
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#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
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vrlw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
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#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
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test_vrlw_7:
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#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
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#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
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vrlw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000002, 00000002, 00000002, 00000002]
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#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
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test_vrlw_8:
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#_ REGISTER_IN v3 [12345678, 87654321, ABCDEF01, FEDCBA98]
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#_ REGISTER_IN v4 [00000008, 00000010, 00000004, 0000000C]
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vrlw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [34567812, 43218765, BCDEF01A, CBA98FED]
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#_ REGISTER_OUT v4 [00000008, 00000010, 00000004, 0000000C]
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test_vrlw_9:
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#_ REGISTER_IN v3 [C0000003, C0000003, C0000003, C0000003]
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#_ REGISTER_IN v4 [00000004, 00000004, 00000004, 00000004]
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vrlw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [0000003C, 0000003C, 0000003C, 0000003C]
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#_ REGISTER_OUT v4 [00000004, 00000004, 00000004, 00000004]
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