xenia-rs/migration/project-root/ppc-manual/alu/extsbx.md

extsbx — Extend Sign Byte

Category: Integer ALU · Form: X · Opcode: 0x7c000774

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
extsb	extsbx	—	Extend Sign Byte
extsb.	extsbx	Rc=1	Extend Sign Byte

Syntax

extsb[Rc] [RA], [RS]

Encoding

extsbx — form X

• Opcode word: 0x7c000774
• Primary opcode (bits 0–5): 31
• Extended opcode: 954
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	extsbx: read	Source GPR (alias for RD in some stores).
RA	extsbx: write	Source GPR (r0–r31).
CR	extsbx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

extsbx

• Reads (always): RS
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• extsbx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- EXTS_8_to_64((RS)[56:63])

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

extsbx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="extsbx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:714
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:25
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:849
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:589-595

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::extsbx => {
            // PPCBUG-034: 32-bit ABI — sign-extend byte to i32, write zero-extended.
            // PPCBUG-036 (coupled): CR0 must view result as i32, not i64.
            ctx.gpr[instr.ra()] = ctx.gpr[instr.rs()] as i8 as i32 as u32 as u64;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Sign-extends the low 8 bits of RS to 64 bits. Bit 56 of RS (the sign bit of the byte) becomes bits 0–55 of RA; bits 56–63 are copied verbatim.
• Common after a byte load. lbz zero-extends from memory; extsb converts the result to a signed-byte view. Many compilers emit this pair; the recent ISA lba/lbau family is not available on the Xenon, so this two-instruction sequence is the canonical pattern.
• Rc=1 updates CR0 from the full 64-bit signed value — but xenia-rs truncates to 32 bits in interpreter.rs:384. For extsb. this is harmless because the result fits in 8 bits sign-extended; the low 32 bits already encode the sign correctly.
• Operand convention is the X-form one (RA destination, RS source). Same as the rest of the logical family.
• No XER side effects.
• RB field unused. Set to 0 by assemblers; ignored on decode.
• Aliasing is fine. extsb r3, r3 rewrites r3 in place.

Related Instructions

• extshx — sign-extend half-word (16 bits).
• extswx — sign-extend word (32 bits).
• rlwinmx, rldiclx — for zero-extending or extracting non-byte-aligned fields.
• lbz, lha (memory ops, outside this page set) — pair with this for signed byte loads.

IBM Reference

• AIX 7.3 — extsb (Extend Sign Byte)