xenia-rs/migration/project-root/ppc-manual/alu/extshx.md

extshx — Extend Sign Half Word

Category: Integer ALU · Form: X · Opcode: 0x7c000734

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
extsh	extshx	—	Extend Sign Half Word
extsh.	extshx	Rc=1	Extend Sign Half Word

Syntax

extsh[Rc] [RA], [RS]

Encoding

extshx — form X

• Opcode word: 0x7c000734
• Primary opcode (bits 0–5): 31
• Extended opcode: 922
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	extshx: read	Source GPR (alias for RD in some stores).
RA	extshx: write	Source GPR (r0–r31).
CR	extshx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

extshx

• Reads (always): RS
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• extshx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- EXTS_16_to_64((RS)[48:63])

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

extshx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="extshx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:727
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:25
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:847
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:596-602

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::extshx => {
            // PPCBUG-035: same shape as extsbx for halfwords.
            // PPCBUG-037 (coupled): CR0 i32 view.
            ctx.gpr[instr.ra()] = ctx.gpr[instr.rs()] as i16 as i32 as u32 as u64;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Sign-extends the low 16 bits of RS to 64 bits. Bit 48 (the sign bit of the half-word) is replicated through bits 0–47 of RA.
• Pairs with lhz to convert an unsigned half-word load into a signed half-word value. Note that lha already does the sign extension on load — extsh is mostly emitted when the half-word is computed in a register first.
• Rc=1 CR0 update. Xenia-rs uses as i32 as i64 (interpreter.rs:389) — harmless here because the sign-extended 16-bit value fits in 32 bits exactly.
• Operand convention is the X-form one (RA destination, RS source).
• No XER side effects.
• RB field unused.
• Aliasing is fine. extsh r3, r3 is the standard "promote r3's low 16 bits to a signed 64-bit value" sequence.

Related Instructions

• extsbx — sign-extend byte.
• extswx — sign-extend word (32 bits).
• rlwinmx — when masking/zero-extending without sign-extension.
• lha (memory op, outside this set) — combined load + sign-extend.

IBM Reference

• AIX 7.3 — extsh (Extend Sign Half Word)