xenia-rs/migration/project-root/ppc-manual/alu/srwx.md

srwx — Shift Right Word

Category: Integer ALU · Form: X · Opcode: 0x7c000430

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
srw	srwx	—	Shift Right Word
srw.	srwx	Rc=1	Shift Right Word

Syntax

srw[Rc] [RA], [RS], [RB]

Encoding

srwx — form X

• Opcode word: 0x7c000430
• Primary opcode (bits 0–5): 31
• Extended opcode: 536
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	srwx: read	Source GPR (alias for RD in some stores).
RB	srwx: read	Source GPR.
RA	srwx: write	Source GPR (r0–r31).
CR	srwx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

srwx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• srwx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

n <- (RB)[58:63]
RA <- ((RS)[32:63] >> n)  zero-extended   if n < 32 else 0

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

srwx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="srwx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:1180
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:65
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:820
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:632-641

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::srwx => {
            // PPCBUG-044: 32-bit ABI CR0 view (zero-extended right shift can never
            // have bit 31 set, but use the canonical form for consistency).
            let sh = ctx.gpr[instr.rb()] as u32;
            ctx.gpr[instr.ra()] = if sh < 32 {
                ((ctx.gpr[instr.rs()] as u32) >> sh) as u64
            } else { 0 };
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• 32-bit logical right shift, zero-extended to 64. RA ← (u32)RS >> (RB & 0x3F) if count < 32, else RA = 0. The high 32 bits of RA are always zero.
• Shift count is 6 bits, RB[58:63]. Counts [32, 63] produce zero (not RS >> (count mod 32)); xenia's explicit if sh < 32 guards against Rust UB (interpreter.rs:425).
• No XER[CA] produced. For arithmetic shift with XER[CA] use srawx.
• Rc=1 CR0 update truncates to 32 bits in xenia-rs. interpreter.rs:428. Since the result has zeroed high 32 bits and zeroed sign bit (high bit of the 32-bit result is always 0 after a non-zero shift), CR0 will be EQ or GT.
• No OE bit.
• srwi simplified mnemonic uses rlwinmx, not this instruction. srw is for runtime-variable counts.

Related Instructions

• srdx — 64-bit logical right shift.
• srawx, srawix — 32-bit arithmetic right.
• slwx — 32-bit left shift.
• rlwinmx — srwi immediate expansion.

IBM Reference

• AIX 7.3 — srw (Shift Right Word)