xenia-rs/migration/project-root/ppc-manual/fpu/faddsx.md

faddsx — Floating Add Single

Category: Floating-Point · Form: A · Opcode: 0xec00002a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fadds	faddsx	—	Floating Add Single
fadds.	faddsx	Rc=1	Floating Add Single

Syntax

fadds[Rc] [FD], [FA], [FB]

Encoding

faddsx — form A

• Opcode word: 0xec00002a
• Primary opcode (bits 0–5): 59
• Extended opcode: 21
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	faddsx: read	Source A floating-point register (fr0–fr31).
FB	faddsx: read	Source B floating-point register.
FD	faddsx: write	Destination floating-point register.
CR	faddsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	faddsx: write	Floating-Point Status and Control Register.

Register Effects

faddsx

• Reads (always): FA, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• faddsx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

FRT <- RoundToSingle(FRA + FRB)          ; single-precision

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

faddsx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="faddsx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:46
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:27
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:388
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2565-2574

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::faddsx => {
            let a = ctx.fpr[instr.ra()];
            let b = ctx.fpr[instr.rb()];
            fpscr::check_invalid_add(ctx, a, b, false);
            let result = to_single(ctx, a + b);
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, a.is_finite() && b.is_finite());
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Single precision via double FPRs. The trailing s in the mnemonic means the result is rounded to IEEE-754 binary32 after the addition, then re-encoded into the 64-bit FPR using the binary64 representation of that single-precision value. The host computes to_single(a + b); both source operands are read as full binary64.
• FPSCR side effects. Hardware updates FPRF (result class), FR/FI (rounding info), FX, and the exception bits — OX on overflow, UX on underflow, XX on inexact, VXISI on ±∞ − ±∞, VXSNAN on a signalling-NaN input. xenia-rs does not maintain FPSCR in the interpreter snapshot — call this out as a xenia quirk if you depend on cross-instruction FPSCR observation.
• Rc=1 (fadds.) copies FPSCR[FX, FEX, VX, OX] into CR1. xenia models this via update_cr1_from_fpscr().
• NaN propagation. Any NaN input yields a quiet NaN result; signalling NaNs are quietened (signalling bit cleared) per PowerISA. Host-native f64 + may not perform that quietening on every platform.
• ±∞ − ±∞ after rounding. Although +-shaped, opposite-signed infinities still produce QNaN(VXISI).
• FPSCR[NI] (non-IEEE / flush-to-zero) is set at Xenon boot, so denormal results normally flush to zero. Xenia inherits host semantics, which is IEEE-compliant by default; titles tuned around flush-to-zero may see slightly different denormal rounding under xenia.
• Rounding mode uses FPSCR[RN] (00 nearest-even, 01 toward 0, 10 toward +∞, 11 toward −∞). Default is nearest-even and is rarely changed.
• A-form encoding ignores FRC. Bits 21–25 are don't-care for the add family.

Related Instructions

• faddx — double-precision sibling.
• fsubsx, fmulsx, fdivsx — other single-precision arithmetic ops.
• fmaddsx, fmsubsx, fnmaddsx, fnmsubsx — fused multiply-add single-precision family (single rounding step).
• frspx — explicit double→single rounding helper; fadds is essentially frsp(fadd) fused into one rounding.
• mffsx, mtfsfx — read/write FPSCR for rounding-mode and exception control.

IBM Reference

• AIX 7.3 — fadds (Floating Add Single)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (single-precision rounding rules and FPSCR side effects).