xenia-rs/migration/project-root/ppc-manual/fpu/fmaddsx.md

fmaddsx — Floating Multiply-Add Single

Category: Floating-Point · Form: A · Opcode: 0xec00003a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fmadds	fmaddsx	—	Floating Multiply-Add Single
fmadds.	fmaddsx	Rc=1	Floating Multiply-Add Single

Syntax

fmadds[Rc] [FD], [FA], [FC], [FB]

Encoding

fmaddsx — form A

• Opcode word: 0xec00003a
• Primary opcode (bits 0–5): 59
• Extended opcode: 29
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fmaddsx: read	Source A floating-point register (fr0–fr31).
FC	fmaddsx: read	Source C floating-point register (for madd-style ops).
FB	fmaddsx: read	Source B floating-point register.
FD	fmaddsx: write	Destination floating-point register.
CR	fmaddsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fmaddsx: write	Floating-Point Status and Control Register.

Register Effects

fmaddsx

• Reads (always): FA, FC, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fmaddsx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fmaddsx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fmaddsx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:190
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:28
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:393
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2653-2665

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fmaddsx => {
            // PPCBUG-181: missing VXISI on add step.
            let a = ctx.fpr[instr.ra()];
            let c = ctx.fpr[instr.rc()];
            let b = ctx.fpr[instr.rb()];
            fpscr::check_invalid_mul(ctx, a, c);
            fpscr::check_invalid_fma_add(ctx, a, c, b, false);
            let result = to_single(ctx, a.mul_add(c, b));
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, a.is_finite() && b.is_finite() && c.is_finite());
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Single rounding step then single-precision rounding. PowerISA semantics: compute (FRA × FRC) + FRB to infinite precision, then round once to binary32. xenia-rs implements this as to_single(a.mul_add(c, b)) — the mul_add is the single-step fused multiply-add at double precision, then to_single rounds the binary64 result to binary32. This matches PPC's "single rounding" requirement because the intermediate mul_add is already exact-rounded.
• Operand order. Assembler: FD, FA, FC, FB (multiplier FRC before addend FRB).
• Invalid operations. 0×∞ + finite → VXIMZ; opposite-signed-∞ collision → VXISI. Quiet NaN result with FPSCR[VX, FX].
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX, OX, UX, XX, VXIMZ, VXISI, VXSNAN. xenia-rs does not (xenia quirk).
• Rc=1 (fmadds.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Single-precision overflow of the final rounded result returns ±∞ and sets OX/XX/FX.
• Use case. Dominates single-precision graphics math: matrix–vector multiplies, dot products, lighting equations, normal-map blending. Xbox 360 titles emit fmadds constantly.
• Denormal flush. Xenon boots with FPSCR[NI]=1; xenia uses host IEEE behavior.

Related Instructions

• fmaddx — double-precision sibling.
• fmsubsx, fnmaddsx, fnmsubsx — single-precision fused-multiply siblings:
  • fmsubs = (A×C) − B
  • fnmadds = −((A×C) + B)
  • fnmsubs = −((A×C) − B)
• fmulsx, faddsx — non-fused decomposition.
• fresx, frsqrtex — reciprocal helpers; Newton-Raphson refinement uses fmadds/fnmsubs.
• frspx — explicit double→single rounding.

IBM Reference

• AIX 7.3 — fmadds (Floating Multiply-Add Single)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.