xenia-rs/migration/project-root/ppc-manual/fpu/fmulx.md

fmulx — Floating Multiply

Category: Floating-Point · Form: A · Opcode: 0xfc000032

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fmul	fmulx	—	Floating Multiply
fmul.	fmulx	Rc=1	Floating Multiply

Syntax

fmul[Rc] [FD], [FA], [FC]

Encoding

fmulx — form A

• Opcode word: 0xfc000032
• Primary opcode (bits 0–5): 63
• Extended opcode: 25
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fmulx: read	Source A floating-point register (fr0–fr31).
FC	fmulx: read	Source C floating-point register (for madd-style ops).
FD	fmulx: write	Destination floating-point register.
CR	fmulx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fmulx: write	Floating-Point Status and Control Register.

Register Effects

fmulx

• Reads (always): FA, FC
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fmulx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

FRT <- FRA × FRC

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fmulx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fmulx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:89
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:28
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:925
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2595-2605

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fmulx => {
            // A-form: frD = frA * frC (frC is at rc() field, bits 21-25)
            let a = ctx.fpr[instr.ra()];
            let c = ctx.fpr[instr.rc()];
            fpscr::check_invalid_mul(ctx, a, c);
            let result = a * c;
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, a.is_finite() && c.is_finite());
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• A-form quirk: multiplier is FRC, not FRB. fmul reads operands from the FRA (bits 11–15) and FRC (bits 21–25) fields, bridging the multiply and fused-multiply-add families. xenia decodes this as instr.rc() (the FRC field, distinct from rc_bit() for the record bit).
• Double precision. Operates on IEEE-754 binary64; fmulsx rounds to binary32.
• 0 × ±∞ is invalid. Sets FPSCR[VXIMZ, VX, FX] and yields a quiet NaN.
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX plus exception bits OX (overflow), UX (underflow), XX (inexact), VXIMZ (0×∞), VXSNAN (signalling NaN). xenia-rs does not update FPSCR in the interpreter snapshot — xenia quirk.
• Rc=1 (fmul.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Any NaN operand yields a quiet NaN; signalling NaNs are quietened.
• Sign of result. Standard IEEE: sign(a) XOR sign(c). +0 × −0 = −0 and −x × +∞ = −∞.
• Denormal flush. Xenon boots with FPSCR[NI]=1 (flush-to-zero); xenia inherits host IEEE behavior, so multiplications that produce subnormal results may differ subtly from hardware.
• Rounding mode uses FPSCR[RN] (default nearest-even).

Related Instructions

• fmulsx — single-precision multiply.
• fmaddx, fmsubx, fnmaddx, fnmsubx — fused multiply-add family; share the same FRA × FRC core but add/subtract FRB with a single rounding step. Prefer fused forms for dot products and polynomial evaluation.
• faddx, fsubx, fdivx — sibling double-precision arithmetic.
• fresx, frsqrtex — reciprocal helpers commonly paired with fmul for reciprocal divides.
• mffsx, mtfsfx — FPSCR control.

IBM Reference

• AIX 7.3 — fmul (Floating Multiply)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.