xenia-rs/migration/project-root/ppc-manual/fpu/fresx.md

fresx — Floating Reciprocal Estimate Single

Category: Floating-Point · Form: A · Opcode: 0xec000030

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fres	fresx	—	Floating Reciprocal Estimate Single
fres.	fresx	Rc=1	Floating Reciprocal Estimate Single

Syntax

fres[Rc] [FD], [FB]

Encoding

fresx — form A

• Opcode word: 0xec000030
• Primary opcode (bits 0–5): 59
• Extended opcode: 24
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FB	fresx: read	Source B floating-point register.
FD	fresx: write	Destination floating-point register.
CR	fresx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fresx: write	Floating-Point Status and Control Register.

Register Effects

fresx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fresx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fresx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fresx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:106
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:29
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:390
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2815-2835

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fresx => {
            // Single-precision reciprocal estimate: frD = 1.0 / frB.
            // PPCBUG-184: pre-quantize input to f32 to match canary's
            // `f.Recip(f.Convert(frB, FLOAT32_TYPE))` behavior. Hardware
            // produces a ~12-bit LUT estimate; both emulators produce a
            // fully-IEEE single reciprocal, but the f32 quantization at
            // least makes the input precision match.
            let b_full = ctx.fpr[instr.rb()];
            let b = b_full as f32 as f64;
            if b == 0.0 {
                fpscr::set_exception(ctx, fpscr::ZX);
            }
            if fpscr::is_snan(b_full) {
                fpscr::set_exception(ctx, fpscr::VXSNAN);
            }
            let result = to_single(ctx, 1.0 / b);
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, b.is_finite() && b != 0.0);
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Single-precision reciprocal estimate. PowerISA specifies a low-precision approximation of 1/FRB accurate to roughly 12–14 bits of significand, intended as the seed for a Newton-Raphson refinement step. xenia quirk: xenia-rs computes the full-precision 1.0 / b then rounds to single, so it produces a far more accurate result than hardware. Title code that depends on the limited precision of fres to trigger refinement loops will still work (the loops just refine an already-correct value), but bit-exact correlation with hardware is impossible.
• Single precision result. Final value is rounded to binary32 then re-encoded into the FPR.
• Divide by zero. 1/±0 → ±∞ and sets FPSCR[ZX, FX]. xenia returns the host ±∞ but does not update FPSCR.
• fres(±∞) = ±0 (correctly signed).
• fres(NaN) = NaN; signalling NaNs are quietened.
• Overflow / underflow. May set OX/UX/XX/FX. xenia does not update FPSCR.
• Rc=1 (fres.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• Encoding. A-form, primary 59, XO 24. Reads FRB only; FRA/FRC are don't-care.
• Use case. Software reciprocal: 1/d ≈ x = fres(d); x = x*(2 - d*x); (one Newton-Raphson step recovers full single precision). Two iterations recover full double precision. The (2 - d*x) step compiles to fnmsub.
• Performance. Cheap on Xenon (single-cycle issue) — divides by fres + 1–2 NR steps + fmul are far faster than fdiv/fdivs.

Related Instructions

• frsqrtex — reciprocal-square-root estimate; same NR refinement approach.
• fdivx, fdivsx — true divide; alternative when refinement isn't needed.
• fnmsubx, fnmsubsx — the workhorse for the (2 - d*x) step.
• fmulx, fmulsx — final multiply to apply the reciprocal.
• fmaddsx — alternate refinement formulation.

IBM Reference

• AIX 7.3 — fres (Floating Reciprocal Estimate Single)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (relative-error bound for fres; intended Newton-Raphson refinement pattern).