xenia-rs/migration/project-root/ppc-manual/fpu/fsqrtx.md

fsqrtx — Floating Square Root

Category: Floating-Point · Form: A · Opcode: 0xfc00002c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fsqrt	fsqrtx	—	Floating Square Root
fsqrt.	fsqrtx	Rc=1	Floating Square Root

Syntax

fsqrt[Rc] [FD], [FB]

Encoding

fsqrtx — form A

• Opcode word: 0xfc00002c
• Primary opcode (bits 0–5): 63
• Extended opcode: 22
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FB	fsqrtx: read	Source B floating-point register.
FD	fsqrtx: write	Destination floating-point register.
CR	fsqrtx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fsqrtx: write	Floating-Point Status and Control Register.

Register Effects

fsqrtx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fsqrtx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fsqrtx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fsqrtx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:164
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:30
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:923
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2786-2800

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fsqrtx => {
            let b = ctx.fpr[instr.rb()];
            // sqrt of negative (non-zero) is invalid operation → VXSQRT.
            if b.is_sign_negative() && b != 0.0 && !b.is_nan() {
                fpscr::set_exception(ctx, fpscr::VXSQRT);
            }
            if fpscr::is_snan(b) {
                fpscr::set_exception(ctx, fpscr::VXSNAN);
            }
            let result = b.sqrt();
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, b.is_finite());
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Double precision. Operates on IEEE-754 binary64; fsqrtsx is the single-precision sibling. xenia delegates to host f64::sqrt.
• Negative inputs are invalid. sqrt(x < 0) (other than -0) sets FPSCR[VXSQRT, VX, FX] and yields a quiet NaN. Note: sqrt(-0) = -0 per IEEE-754 (preserves sign of zero) — host f64::sqrt matches.
• sqrt(+∞) = +∞, exact.
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX plus exception bits XX (inexact, very common since sqrt is rarely exact), VXSQRT, VXSNAN. xenia-rs does not update FPSCR (xenia quirk).
• Rc=1 (fsqrt.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Performance / availability. fsqrt is a Power-ISA optional instruction; some implementations trap as illegal-opcode. Xenon implements it natively. xenia-rs supports it directly.
• Encoding. A-form, primary 63, XO 22; reads FRB only — FRA and FRC are don't-care.
• Rounding mode uses FPSCR[RN].

Related Instructions

• fsqrtsx — single-precision square root.
• frsqrtex — reciprocal-square-root estimate (~1/sqrt(x)); preferred for normalize/length operations.
• fresx — reciprocal estimate; pairs with fsqrt for 1/sqrt(x).
• fmulx, fmaddx — used in Newton-Raphson refinement of frsqrte outputs.
• mffsx, mtfsfx — FPSCR control.

IBM Reference

• AIX 7.3 — fsqrt (Floating Square Root)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (square-root invalid-operation rules).